DETAILED ACTION
This action is responsive to the election received on 05/11/2026
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figure 9) in the reply filed on 05/11/2026 is acknowledged. Claim(s) 23 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/11/2026.
Claim 23 includes the requirement of “the two jumpers are offset from each other” in the claim language. This limitation is interpreted to read on Figure 11 (non-elected species B) or Figure 12 (non-elected species C) based on both figures including 1st and 2nd jumpers which are offset from one another as described in [0019] and [0044] of the instant application’s specification. In contrast, elected Figure 9 includes a double jumper, which may be interpreted as comprising two jumpers, which are not offset from one another as they are directly in line as a singular double jumper structure.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/06/2023 and 02/06/2025 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claim(s) 24-25 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 24, line 3, “forming an interconnect located on the underlying device” as without this change, it is unclear what the adjective ‘interconnected’ is describing.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-12, 15-20, and 24-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,978,438 B1; Lam et al.; 04/2021; (“Lam”).
Regarding Claim 1. Lam discloses A microelectronic structure (Figure 7, monolithic integrated circuit structure) comprising:
an underlying device (Figure 7, control elements);
an interconnect (Figure 7, interconnect and connector stacks) located on the underlying device (Figure 7, the interconnect and connector stacks are on the control elements), wherein the interconnect comprises:
a first Mx metal line (Figure 7, left m1) and a second Mx metal line (Figure 7, right m1), wherein the first Mx metal line is located adjacent to the second Mx metal line (Figure 7, left and right m1s are adjacent to one another); and
a jumper (Figure 7, interconnect jumper) connects the first Mx metal line to the second Mx metal line (Figure 7, the interconnect jumper electrically connects the left and right m1s), wherein the first Mx metal line extends higher than the jumper (Figure 7, both the left and right m1s extend to a higher vertical level than the interconnect jumper).
Regarding Claim 2. Lam discloses The microelectronic structure of claim 1, wherein the jumper is located at a base of the first Mx metal line and at a base of the second Mx metal line (Figure 7, the interconnect jumper is located at a base, or bottom, of both the left and right m1s).
Regarding Claim 3. Lam discloses The microelectronic structure of claim 1, further comprising: a first layer (Figure 7, control element jumper) located between the underlying device and the first Mx metal line (Figure 7, the control element jumper is located physically between the left m1 and the right control element), and the first layer is located between the underlying device and the second Mx metal line (Figure 7, the control element jumper is located physically between the right m1 and the right control element).
Regarding Claim 6. Lam discloses The microelectronic structure of claim 1, wherein the interconnect further comprises: an interlayer dielectric layer (Figure 7, wiring and interconnect via layers which are necessarily dielectrics or the separate wiring lines would be shorted) located above and around the first Mx metal line, the second Mx metal line, and the jumper (Figure 7, the combination of the wiring and interconnect via layers are located above and around, at least partially, the left and right m1s and the interconnect jumper).
Regarding Claim 7. Lam discloses The microelectronic structure of claim 6, wherein the interconnect further comprises: a Mx+1 metal line (Figure 7, left and right m2s) located on top of the interlayer dielectric layer (Figure 7, the left and right m2s are located on top of the interconnect via layer).
Regarding Claim 8. Lam discloses The microelectronic structure of claim 7, wherein the first Mx metal line, the second Mx metal line, and the jumper are located at a different height than the Mx+1 metal line (Figure 7, the left and right m1s, the left and right m2s, and the interconnect jumper are all located at different vertical levels).
Regarding Claim 9. Lam discloses The microelectronic structure of claim 8, wherein the interlayer dielectric layer is located between the Mx+1 metal line and the first Mx metal line, the second Mx metal line, and the jumper (Figure 7, the combination of the wiring layer and the interconnect via layer is located physically, at least partially, between the left and right m1s, the left and right m2s, and the interconnect jumper).
Regarding Claim 10. Lam discloses A microelectronic structure (Figure 7, monolithic integrated circuit structure) comprising:
an underlying device (Figure 7, control elements);
an interconnect (Figure 7, interconnect and connector stacks) located on the underlying device (Figure 7, the interconnect and connector stacks are on the control elements), wherein the interconnect comprises:
a plurality of Mx metal lines (Figure 7, left and right m1s and m2s), wherein at least one Mx metal line of the plurality of Mx Metal lines includes an integral connecting via (Figure 7, both of the left and right m2s may be interpreted as including their overlying integral vias, v2s, respectively); and
at least one jumper (Figure 7, interconnect jumper) connecting at least two adjacent Mx metal lines of the plurality of Mx metal lines (Figure 7, the interconnect jumper electrically connects the left and right m1s), wherein the at least one Mx metal line with the integral connecting via extends higher than the at least two adjacent Mx metal lines (Figure 7, the m2s with their v2s extend higher than the left and right m1s).
Regarding Claim 11. Lam discloses The microelectronic structure of claim 10, wherein the at least one jumper is located at a base of the at least two adjacent Mx metal lines Figure 7, the interconnect jumper is located at a base, or bottom, of both the left and right m1s).
Regarding Claim 12. Lam discloses The microelectronic structure of claim 10, further comprising: a first layer (Figure 7, control element jumper) located between the underlying device and the at least two adjacent Mx metal lines (Figure 7, the control element jumper is located physically between the left m1 and the right control element and the control element jumper is located physically between the right m1 and the right control element).
Regarding Claim 15. Lam discloses The microelectronic structure of claim 10, wherein the interconnect further comprises: an interlayer dielectric layer (Figure 7, wiring and interconnect via layers which are necessarily dielectrics or the separate wiring lines would be shorted) located above and around the at least one jumper and the at least two adjacent Mx metal lines (Figure 7, the combination of the wiring and interconnect via layers are located above and around, at least partially, the left and right m1s and the interconnect jumper).
Regarding Claim 16. Lam discloses The microelectronic structure of claim 15, wherein the interconnect further comprises: at least one Mx+1 metal line (Figure 7, left and right m3s) located on top of the interlayer dielectric layer (Figure 7, the left and right m3s are located on top of the interconnect via layer where “on” does not require direct contact).
Regarding Claim 17. Lam discloses The microelectronic structure of claim 16, wherein the at least one jumper and the at least two adjacent Mx metal lines are located at a different height than the at least one Mx+1 metal line (Figure 7, the left and right m1s, the left and right m3s, and the interconnect jumper are all located at different vertical levels).
Regarding Claim 18. Lam discloses The microelectronic structure of claim 17, wherein the interlayer dielectric layer is located between the at least one Mx+1 metal line and the at least one jumper and the at least two adjacent Mx metal lines.
Regarding Claim 19. Lam discloses The microelectronic structure of claim 18, wherein the at least one Mx+1 metal line is connected to a top surface of the at least one Mx metal line that includes the integral connecting via (Figure 7, the left and right m3s are electrically connected to a top surface of their underlying m2s with their respective integral v2s).
Regarding Claim 20. Lam discloses A microelectronic structure (Figure 7, monolithic integrated circuit structure) comprising:
an underlying device (Figure 7, control elements);
an interconnect (Figure 7, interconnect and connector stacks) located on the underlying device (Figure 7, the interconnect and connector stacks are on the control elements), wherein the interconnect comprises:
a plurality of Mx metal lines (Figure 7, left and right m1s, left and right m2s, and left and right m3s); and
at least one or more jumpers (Figure 7, interconnect jumper) connecting a group Mx metal lines of the plurality of Mx metal lines (Figure 7, the interconnect jumper connects m1-m3 on the left with m1 -m3 on the right),
wherein the group of Mx metal lines includes three adjacent Mx metal lines (Figure 7, the group includes at least m1-m3 on the left), wherein each of the Mx metal lines in the group of Mx metal lines extends higher than the at least one or more jumpers (Figure 7, all of the m1-m3 lines extend higher than the interconnect jumper).
Regarding Claim 24. Lam discloses A method (Figure 7, monolithic integrated circuit structure, column 39, line 40 through column 40 line 65 describe related method steps) comprising:
forming an underlying device (Figure 7, control elements which are necessarily formed);
forming an interconnect (Figure 7, interconnect and connector stacks which are necessarily formed) located on the underlying device (Figure 7, the interconnect and connector stacks are on the control elements), wherein the interconnect comprises:
a first Mx metal line (Figure 7, left m1) and a second Mx metal line (Figure 7, right m1), wherein the first Mx metal line is located adjacent to the second Mx metal line (Figure 7, left and right m1s are adjacent to one another); and
a jumper (Figure 7, interconnect jumper) connects the first Mx metal line to the second Mx metal line (Figure 7, the interconnect jumper electrically connects the left and right m1s), wherein the first Mx metal line extends higher than the jumper (Figure 7, both the left and right m1s extend to a higher vertical level than the interconnect jumper).
Regarding Claim 25. Lam discloses The method of claim 24, wherein the jumper is located at a base of the first Mx metal line and at a base of the second Mx metal line (Figure 7, the interconnect jumper is located at a base, or bottom, of both the left and right m1s).
Claim(s) 1, 3-5, 10, and 12-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0167106 A1; Choi et al.; 05/2025; (“Choi”).
Regarding Claim 1. Choi discloses A microelectronic structure (#10, Figures 1A-1D, interconnect structure) comprising:
an underlying device (#100, Figures 1b-1D, base layer which may include a transistor structure therein according to [0033]);
an interconnect (Figures 1B-1D, structures above L0) located on the underlying device (Figures 1B-1D, the structures above L0 re located on #100), wherein the interconnect comprises:
a first Mx metal line (#M31 between L1 and L2, Figure 1D, part of metal line structure) and a second Mx metal line (#M32 between L1 and L2, Figure 1D, part of metal line structure), wherein the first Mx metal line is located adjacent to the second Mx metal line (Figures 1A-1D the metal lines are all adjacent to one another); and
a jumper connects the first Mx metal line to the second Mx metal line (portions of #M31 and #M32 between L0 and L1, Figure 1A metal line structure connecting the two metal line structures between L1 and L2), wherein the first Mx metal line extends higher than the jumper (Figure 1D, the metal line structures between L1 and L2 extend higher than the jumper below L1).
Regarding Claim 3. Choi discloses The microelectronic structure of claim 1, further comprising: a first layer (#101, Figures 1B-1D) located between the underlying device and the first Mx metal line (Figure 1D, #101 is located between #100 and the metal line of #M31), and the first layer is located between the underlying device and the second Mx metal line (Figure 1D, #101 is located between #100 and the metal line of #M32).
Regarding Claim 4. Choi discloses The microelectronic structure of claim 3, wherein the first layer is comprised of TiN or TaN ([0036], #101 may be made of TiN or TaN).
Regarding Claim 5. Choi discloses The microelectronic structure, of claim 4 wherein the jumper is located on the first layer (Figures 1D, the jumper structure of #M31 and #M32 between L0 and L1 is located on #101).
Regarding Claim 10. Choi discloses A microelectronic structure (#10, Figures 1A-1D, interconnect structure) comprising:
an underlying device (#100, Figures 1B-1D, base layer which may include a transistor structure therein according to [0033]);
an interconnect (Figures 1B-1D, structures above L0) located on the underlying device (Figures 1B-1D, the structures above L0 re located on #100), wherein the interconnect comprises:
a plurality of Mx metal lines (#M1-#M6, Figure 1A, metal lines), wherein at least one Mx metal line of the plurality of Mx Metal lines includes an integral connecting via (Figure 1D, #M31 has an integral via #V1); and
at least one jumper (portions of #M31 and #M32 between L0 and L1, Figure 1A metal line structure connecting the two metal line structures between L1 and L2) connecting at least two adjacent Mx metal lines of the plurality of Mx metal lines (Figures 1A and 1C, the metal jumper structure forms at least part of a physical connection between #M2 and #M4 on opposing sides of #M3), wherein the at least one Mx metal line with the integral connecting via extends higher than the at least two adjacent Mx metal lines (Figure 1C, #M32 including #V1 extends to a greater vertical height than #M2 and #M4).
Regarding Claim 12. Choi discloses The microelectronic structure of claim 10, further comprising: a first layer (#101, Figures 1B-1D) located between the underlying device and the at least two adjacent Mx metal lines (Figure 1C, #101 is located between #100 and the metal line of #M2 and #M4).
Regarding Claim 13. Choi discloses The microelectronic structure of claim 12, wherein the first layer is comprised of TiN or TaN ([0036], #101 may be made of TiN or TaN).
Regarding Claim 14. Choi discloses The microelectronic structure of claim 13, wherein the at least one jumper is located on the first layer (Figures 1D, the jumper structure of #M31 and #M32 between L0 and L1 is located on #101).
Claim(s) 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,096,544 B2; Lai et al.; 10/2018; (“Lai”).
Regarding Claim 20. Lai discloses (#400, Figure 10, interconnect structure) A microelectronic structure comprising:
an underlying device (#210, Figure 9, column 8 lines 36-51 and column 4 lines 8-15, Figure 10 is a top view of the via structure which may be formed on a substrate as shown in Figure 9 which includes FET transistor devices therein);
an interconnect (#410-#430, Figure 10,plurality of metal lines and vias) located on the underlying device (Figures 9 and 10, the via structures are on #210), wherein the interconnect comprises:
a plurality of Mx metal lines (#430s, Figure 10, metal vias); and
at least one or more jumpers (#410s, Figure 10, first layer, Mx, metal lines) connecting a group Mx metal lines of the plurality of Mx metal lines (Figure 10, the central #410 connects at least three different #430s),
wherein the group of Mx metal lines includes three adjacent Mx metal lines (Figure 10, the three #430s on the central #410 are three adjacent #430s), wherein each of the Mx metal lines in the group of Mx metal lines extends higher than the at least one or more jumpers (column 8, lines 48-51, the #430s extend from #410 up to #420, i.e. they extend to a higher vertical level than #410).
Regarding Claim 21. Lai discloses The microelectronic structure of claim 20, wherein the at least one or more jumpers is a double jumper (Figure 10, the central #410 is a double jumper in that it forms a double connection to the central #430 thereon to the two opposing adjacent #430s), wherein the double jumper extends laterally to connect the three adjacent Mx metal lines of the group of Mx metal lines (Figure 10, the central #410 extends laterally to connect the three adjacent #430s).
Regarding Claim 22. Lai discloses The microelectronic structure of claim 20, wherein the at least one or more jumpers is comprised of two jumpers to connect the three adjacent Mx metal lines of the group of Mx metal lines (Figure 10, the central #410 may be interpreted as comprising two separate jumpers, one connecting the central #430 to the right #430 thereon and one connecting the central #430 to the left #430 thereon).
Claim(s) 1-5 and 10-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,094,580 B2; Park et al.; 08/2021; (“Park”).
Regarding Claim 1. Park discloses A microelectronic structure (#100, Figure 8, semiconductor structure) comprising:
an underlying device (#102, Figure 8, base which may include various devices according to column 5 lines 13-16);
an interconnect (#104, #112, and #116, Figure 8, metal lines, metal layers, and metal lines) located on the underlying device (Figure 8, #104, #112, and #116 are located on #102), wherein the interconnect comprises:
a first Mx metal line (#112 middle front, Figure 8, front center metal layer) and a second Mx metal line (#112 middle back, Figure 8, back center metal layer), wherein the first Mx metal line is located adjacent to the second Mx metal line (Figure 8, all #112s are adjacent to one another); and
a jumper (#104, Figure 8, metal line) connects the first Mx metal line to the second Mx metal line (Figures 8-9, #104 connects the front and back center #112s), wherein the first Mx metal line extends higher than the jumper (Figures 8-9, #112s extend higher than #104).
Regarding Claim 2. Park discloses The microelectronic structure of claim 1, wherein the jumper is located at a base of the first Mx metal line and at a base of the second Mx metal line (Figures 8-9, #104 is located at a base of the #112s).
Regarding Claim 3. Park discloses The microelectronic structure of claim 1, further comprising: a first layer (#106, Figure 8, etch stop layer) located between the underlying device and the first Mx metal line, and the first layer is located between the underlying device and the second Mx metal line (Figures 8-9, #106 is located between the #112s and #102).
Regarding Claim 4. Park discloses The microelectronic structure of claim 3, wherein the first layer is comprised of TiN or TaN (column 5, lines 32-34, “Suitable materials for etch stop layer 106 include, for example . . .TaN”).
Regarding Claim 5. Park discloses The microelectronic structure, of claim 4 wherein the jumper is located on the first layer (Figure 8, #104 is located on #106 where “on” does not require a direction or direct contact).
Regarding Claim 10. Park discloses A microelectronic structure (#100, Figure 8, semiconductor structure) comprising:
an underlying device (#102, Figure 8, base which may include various devices according to column 5 lines 13-16);
an interconnect (#104, #112, and #116, Figure 8, metal lines, metal layers, and metal lines) located on the underlying device (Figure 8, #104, #112, and #116 are located on #102), wherein the interconnect comprises:
a plurality of Mx metal lines (#112s, Figure 8, metal layers), wherein at least one Mx metal line of the plurality of Mx Metal lines includes an integral connecting via (#116, Figure 8, metal line which may be interpreted as integral with the front left #112); and
at least one jumper (#104, Figure 8, metal line) connecting at least two adjacent Mx metal lines of the plurality of Mx metal lines (Figures 8-9, #104 connects the front and back center #112s), wherein the at least one Mx metal line with the integral connecting via extends higher than the at least two adjacent Mx metal lines (Figure 8, the front left #112 with the integral #116 extends higher than the other #112s individually).
Regarding Claim 11. Park discloses The microelectronic structure of claim 10, wherein the at least one jumper is located at a base of the at least two adjacent Mx metal lines (Figures 8-9, #104 is located at a base of the #112s).
Regarding Claim 12. Park discloses The microelectronic structure of claim 10, further comprising: a first layer (#106, Figure 8, etch stop layer) located between the underlying device and the at least two adjacent Mx metal lines (Figures 8-9, #106 is located between the #112s and #102).
Regarding Claim 13. Park discloses The microelectronic structure of claim 12, wherein the first layer is comprised of TiN or TaN (column 5, lines 32-34, “Suitable materials for etch stop layer 106 include, for example . . .TaN”).
Regarding Claim 14. Park discloses The microelectronic structure of claim 13, wherein the at least one jumper is located on the first layer (Figure 8, #104 is located on #106 where “on” does not require a direction or direct contact).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0280456 A1; Huang et al.; 09/2021 – Figure 8 discloses a jumper for interconnecting overlying metal vias which are all made from the same metal material (see Figure 2).
US 2020/0343137 A1; Tien et al.; 10/2020 – Figure 8 discloses a jumper metal line (#129) for interconnecting overlying metal vias (#132s and #136s) along with underlying metal vias (#116s) located in different metallization layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J WIEGAND/Examiner, Art Unit 2812
Prosecution Insights