Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendments filed April 1, 2026.
Claim 11 has been amended.
Claims 1-17 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki (US20070022229A1) in further view of Noble et al. (US11144358B1).
Regarding claim 1, Sasaki teaches a multi-host system comprising:
a first motherboard comprising a first baseboard management controller (BMC) and a first complex programmable logic device (CPLD), the first BMC electrically connected to the first CPLD … (Referring to FIG. 2, the operation and standby system 100 includes an operation controlling apparatus 10 ... The operation controlling apparatus 10 includes a service processor 101 ... a main controller 103)([0025] and [0026]; Figure 2 – a first motherboard (i.e., apparatus 10) including an electrically connected first BMC (i.e., main controller 103) and first CPLD (i.e., logic processor 101) is shown); and
a second motherboard comprising a second BMC and a second CPLD, the second BMC electrically connected to the second CPLD, and the second CPLD electrically connected to the first CPLD … (Referring to FIG. 2, the operation and standby system 100 includes … a standby controlling apparatus 20 ... The standby controlling apparatus 20 includes a service processor 201 ... a main controller 203)([0025] and [0028]; Figure 2 – a second motherboard (i.e., apparatus 20) including an electrically connected second BMC (i.e., main controller 203) and second CPLD (i.e., logic processor 201) which connects to logic processor 101 is shown).
Although Sasaki discloses of using a logic processor to monitor the controller for error (The service processor 101 monitors the main controller 103 through the serial bus 43 and the serial bus 44 (S2). When no error ... the service processor 101 sends a command which orders to toggle the heartbeat signal 208 to the serial controller 204 of the standby controlling apparatus 20 … When the service processor 101 of the operation controlling apparatus 10 detects an error with the main controller 103 ... the service processor 101 stops sending the command ordering to toggle the heartbeat signal (S9))([0039] and [0043]), Sasaki differs from the claim in that Sasaki fails to teach the controllers transmit control signals to the logic processors at time intervals, wherein the first controller is determined to be the main controller based on the first logic processor receiving the first control signal from the first controller and a first signal from the second logic processor and wherein the first logic processor outputs a second signal to the second logic processor.
However, transmitting control signals from controllers to logic processors at time intervals, wherein a first controller is determined to be a main controller based on a first logic processor receiving a first control signal from the first controller and a first signal from a second logic processor and wherein the first logic processor outputs a second signal to the second logic processor is taught by Noble (FIG. 5 shows an exemplary configuration 500 of state control circuits ... state control circuit 404-1 … Watchdog timer 508-1 ... a timer output 512-1 … Gate 514-1 includes inputs coupled to master input 504-1 and a timer output 512-2 from a watchdog timer 508-2 of state control circuit 404-2 ... state control circuit 404-1 may receive a request master signal from controller 402-1 via master input 504-1. The request master signal may indicate a request for controller 402-1 to operate in the master state ... Gate 514-1 may allow the request master signal to pass through ... to watchdog timer 508-1 based on the timer output signal from watchdog timer 508-2 … Each controller may be configured to send periodic request master signals)(column 47 lines 43-52, column 48 lines 28-35, and column 50 lines 1-2; Figure 5 – a first controller is determined to be a main (i.e., master) controller based on a first logic processor (i.e., state control 404-1) receiving a control signal (i.e., master 504-1) from the first controller and a signal from a second logic processor (i.e., timer output 512-2 from state control 404-2) such that the first logic processor outputs a signal (i.e., timer output 512-1) to the second logic processor; the examiner notes a watchdog outputs a high signal (i.e., ‘1’) when not expired and a low signal (i.e., ‘0’) when expired, thus an AND gate with one inverted input will cause the first logic processor to output a second (i.e., high) signal when the control signal is received from the first controller and a first (i.e., low) signal is received from the second logic processor).
The examiner notes Sasaki and Noble teach determining a main controller. As such, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki to include the transmitting of Noble such that control signals are transmitted from controllers to logic processors at time intervals to determine a main controller by a first logic processor receiving a first control signal from a first controller and a first signal from a second logic processor such that the first logic processor outputs a second signal to the second logic processor. One would be motivated to make such a combination to provide the advantage of improving system reliability by dynamically balancing loads between controllers.
Regarding claim 2, Sasaki-Noble teach the multi-host system of claim 1, wherein when the second CPLD receives the second control request signal from the second BMC and the second signal from the first CPLD, the second BMC is determined to be a backup controller of the multi-host system (Noble - the first timer status signal indicates that the first watchdog timer is unexpired when the second request master signal is received by the second state control circuit, the gated combination of the second request master signal and the first timer status signal causes the second watchdog timer to remain expired ... the second controller is to continue operating in the standby state)(column 45 lines 29-37; when the second logic processor receives a control signal from a second controller and the high signal is received from the first logic processor, the second controller is in a backup (i.e., standby) state).
Regarding claim 3, Sasaki-Noble teach the multi-host system of claim 1, wherein when the first BMC stops working, the first CPLD outputs the first signal to the second CLPD, and when the second CPLD receives the second control request signal from the second BMC and the first signal from the first CPLD, the second BMC is determined to be the main controller of the multi-host system (Noble - If the first state control circuit stops receiving the first request master signal from the first controller (e.g., due to malfunction of the first controller) ... the first watchdog timer will expire, thereby causing the first controller to lose mastership ... allowing the second controller to obtain mastership)(column 45 lines 57-63; when the first controller fails the first logic processor sends the low signal, the low signal combined with the control signal received from a second controller the second logic processor sets the second controller as master).
Regarding claim 4, Sasaki-Noble teach the multi-host system of claim 1, wherein the first CPLD comprises a first interface and a second interface, the second CPLD comprises a first interface and a second interface, the first interface of the first CPLD is electrically connected to the second interface of the second CPLD, and the first interface of the second CPLD is electrically connected to the second interface of the first CPLD (although Sasaki discloses of logic processors having interfaces (Referring to FIG. 2, the operation and standby system 100 includes an operation controlling apparatus 10 ... a standby controlling apparatus 20 ... The backplane 30 includes a serial bus 41)([0025] and [0026]; Figure 2 – logic processors being connected though a bus interface is shown). Sasaki does not explicitly teach connecting a first interface of the first logic processor to a second interface of the second logic processor and connecting a first interface of the second logic processor to a first interface of the first logic processor. However, connecting a first interface of a first logic processor to a second interface of a second logic processor and connecting a first interface of the second logic processor to a first interface of the first logic processor is taught by Noble (FIG. 5 shows an exemplary configuration 500 of state control circuits … Gate 514-1 includes inputs coupled to master input 504-1 and a timer output 512-2 from a watchdog timer 508-2 of state control circuit 404-2 ... State control circuit 404-2 further includes a gate 514-2, which receives inputs from master input 504-2 and timer output 512-2)(column 47 lines 43-44, lines 49-52, and lines 64-66; Figure 5 - the first logic processor includes a first interface (i.e., output of timer 508-1) connected a second interface of the second logic processor (i.e., input of gate 514-2) and a second interface (i.e., input of gate 514-1) connected a first interface of the second logic processor (i.e., output of timer 508-2). The examiner notes Sasaki and Noble teach determining a main controller. As such, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki to include the connecting of Noble such that a first interface of a first logic processor is connected to a second interface of a second logic processor and a first interface of the second logic processor is connected to a second interface of the first logic processor. One would be motivated to make such a combination to provide the advantage of improving system reliability by dynamically balancing loads between controllers).
Regarding claim 5, Sasaki-Noble teach the multi-host system of claim 4, wherein when the first CPLD receives the first control request signal from the first BMC and the second interface of the first CPLD receives the first signal outputted by the first interface of the second CPLD, the first BMC is determined to be the main controller of the multi-host system, and the first interface of the first CPLD outputs a second signal to the second interface of the second CPLD (Noble - FIG. 5 shows an exemplary configuration 500 of state control circuits ... state control circuit 404-1 … Watchdog timer 508-1 ... a timer output 512-1 … Gate 514-1 includes inputs coupled to master input 504-1 and a timer output 512-2 from a watchdog timer 508-2 of state control circuit 404-2 ... state control circuit 404-1 may receive a request master signal from controller 402-1 via master input 504-1. The request master signal may indicate a request for controller 402-1 to operate in the master state ... Gate 514-1 may allow the request master signal to pass through ... to watchdog timer 508-1 based on the timer output signal from watchdog timer 508-2)(column 47 lines 43-52 and column 48 lines 28-35; Figure 5 – the first logic processor receives a control signal from the first controller (i.e., master 504-1) and the low signal from the first interface of the second logic processor (i.e., timer output 512-2 from timer 508-2) on the second interface (i.e., input of gate 514-1) to determine the first controller is master and the first logic processor outputs the high signal (i.e., timer output 512-1) using the first interface (i.e., output of timer 508-1) to the second interface of the second logic processor (i.e., input of gate 514-2)).
Regarding claim 6, Sasaki-Noble teach the multi-host system of claim 4, wherein when the second CPLD receives the second control request signal from the second BMC and the second interface of the second CPLD receives the second signal from the first interface of the first CPLD, the second BMC is determined to be a backup controller of the multi-host system (Noble - the first timer status signal indicates that the first watchdog timer is unexpired when the second request master signal is received by the second state control circuit, the gated combination of the second request master signal and the first timer status signal causes the second watchdog timer to remain expired ... the second controller is to continue operating in the standby state … FIG. 5 shows an exemplary configuration 500 of state control circuits)(column 45 lines 29-37 and column 47 lines 43-44; Figure 5 - the second logic processor receives a control signal from the second controller (i.e., master 504-2) and the high signal from the first interface of the first logic processor (i.e., timer output 512-1 from timer 508-1) on the second interface (i.e., input of gate 514-2) to determine the second controller is in backup (i.e., standby) state).
Regarding claim 7, Sasaki-Noble teach the multi-host system of claim 4, wherein when the first BMC stops working, the first interface of the first CPLD outputs the first signal to the second interface of the second CLPD, and when the second CPLD receives the control request signal from the second BMC and the first signal from the first interface of the first CPLD, the second BMC is determined to be the main controller of the multi-host system (Noble - If the first state control circuit stops receiving the first request master signal from the first controller (e.g., due to malfunction of the first controller) ... the first watchdog timer will expire, thereby causing the first controller to lose mastership ... allowing the second controller to obtain mastership … FIG. 5 shows an exemplary configuration 500 of state control circuits)(column 45 lines 57-63 and column 47 lines 43-44; Figure 5 - when the first controller fails the first logic processor sends the low signal from the first interface of the first logic processor (i.e., timer output 512-1 from timer 508-1) to the second interface (i.e., input of gate 514-2) of the second logic processor, the low signal combined with the control signal received from a second controller the second logic processor sets the second controller as master).
Regarding claim 8, Sasaki-Noble teach the multi-host system of claim 4, wherein when a time for the first interface of the first CPLD to output the second signal is greater than a predetermined time, the first interface of the first CPLD outputs the first signal to the second interface of the second CPLD (Noble - Each state control circuit may include a watchdog timer with an expiration state that is either expired or unexpired. Depending on the expiration states of the watchdog timers, the state control circuits may determine which of the controllers is operating in the master state)(column 44 lines 50-55; when time to output the high unexpired signal passes (i.e., expires), the low signal is output).
Regarding claim 9, Sasaki-Noble teach the multi-host system of claim 4, wherein when the first CPLD does not receive the first control request signal of the first BMC after a predetermined time, and the first interface of the first CPLD outputs the first signal to the second interface of the second CPLD (Noble - If the first state control circuit stops receiving the first request master signal from the first controller (e.g., due to malfunction of the first controller) for a predetermined time period, the first watchdog timer will expire)(column 45 lines 57-60).
Regarding claim 10, Sasaki-Noble teach the multi-host system of claim 1, wherein the first BMC is connected to the first CPLD through an inter-integrated circuit (I2C) bus, and the second BMC is connected to the second CPLD through the I2C bus (Sasaki - General-purpose interfaces such as I2C can be applied to the serial buses)([0030]).
Regarding method claims 11-13, the claims generally correspond to system claims 1-3, respectively, and recite similar features in method form; therefore, the claims are rejected under similar rational.
Regarding claim 14, Sasaki-Noble teach the method of claim 11, further comprising:
outputting the first signal to a second interface of the second CPLD by a first interface of the first CPLD when a time for the first interface of the first CPLD to output the second signal is greater than a predetermined time (although Sasaki discloses of logic processors having interfaces (Referring to FIG. 2, the operation and standby system 100 includes an operation controlling apparatus 10 ... a standby controlling apparatus 20 ... The backplane 30 includes a serial bus 41)([0025] and [0026]; Figure 2 – logic processors being connected though a bus interface is shown). Sasaki does not explicitly teach connecting a first interface of the first logic processor to a second interface of the second logic processor to enable the first logic processor to output the low signal when time to output the high signal is greater than a period of time. However, connecting a first interface of a first logic processor to a second interface of a second logic processor to enable the first logic processor to output the low signal when time to output the high signal is greater than a period of time is taught by Noble (Each state control circuit may include a watchdog timer with an expiration state that is either expired or unexpired. Depending on the expiration states of the watchdog timers, the state control circuits may determine which of the controllers is operating in the master state … FIG. 5 shows an exemplary configuration 500 of state control circuits … Gate 514-1 includes inputs coupled to master input 504-1 and a timer output 512-2 from a watchdog timer 508-2 of state control circuit 404-2 ... State control circuit 404-2 further includes a gate 514-2, which receives inputs from master input 504-2 and timer output 512-2)(column 44 lines 50-55, column 47 lines 43-44, lines 49-52, and lines 64-66; Figure 5 - the first logic processor includes a first interface (i.e., output of timer 508-1) connected a second interface of the second logic processor (i.e., input of gate 514-2) to enable the first logic processor to output the low signal when time to output the high unexpired signal passes (i.e., expires)). The examiner notes Sasaki and Noble teach determining a main controller. As such, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki to include the connecting of Noble such that a first interface of a first logic processor is connected to a second interface of a second logic processor to enable the first logic processor to output the low signal when time to output the high signal is greater than a period of time. One would be motivated to make such a combination to provide the advantage of improving system reliability by dynamically balancing loads between controllers).
Regarding claim 15, Sasaki-Noble teach the method of claim 11, further comprising:
outputting the first signal to a second interface of the second CPLD by a first interface of the first CPLD when the first CPLD does not receive the first control request signal of the first BMC after a predetermined time (although Sasaki discloses of logic processors having interfaces (Referring to FIG. 2, the operation and standby system 100 includes an operation controlling apparatus 10 ... a standby controlling apparatus 20 ... The backplane 30 includes a serial bus 41)([0025] and [0026]; Figure 2 – logic processors being connected though a bus interface is shown). Sasaki does not explicitly teach connecting a first interface of the first logic processor to a second interface of the second logic processor to enable the first logic processor to output the low signal when control signal is not received from the first controller after a period of time. However, connecting a first interface of a first logic processor to a second interface of a second logic processor to enable the first logic processor to output the low signal when control signal is not received from the first controller after a period of time is taught by Noble (If the first state control circuit stops receiving the first request master signal from the first controller (e.g., due to malfunction of the first controller) for a predetermined time period, the first watchdog timer will expire … FIG. 5 shows an exemplary configuration 500 of state control circuits … Gate 514-1 includes inputs coupled to master input 504-1 and a timer output 512-2 from a watchdog timer 508-2 of state control circuit 404-2 ... State control circuit 404-2 further includes a gate 514-2, which receives inputs from master input 504-2 and timer output 512-2)(column 45 lines 57-60, column 47 lines 43-44, lines 49-52, and lines 64-66; Figure 5 - the first logic processor includes a first interface (i.e., output of timer 508-1) connected a second interface of the second logic processor (i.e., input of gate 514-2) to enable the first logic processor to output the low signal when signal is not received from the first controller after a period of time). The examiner notes Sasaki and Noble teach determining a main controller. As such, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Sasaki to include the connecting of Noble such that a first interface of a first logic processor is connected to a second interface of a second logic processor to enable the first logic processor to output the low signal when control signal is not received from the first controller after a period of time. One would be motivated to make such a combination to provide the advantage of improving system reliability by dynamically balancing loads between controllers).
Regarding claim 16, Sasaki-Noble teach the method of claim 11, wherein the first signal is a low-level signal, and the second signal is a high-level signal (Noble - The first state control circuit includes a first watchdog timer and the second state control circuit includes a second watchdog timer)(column 44 lines 59-62; as previously noted a watchdog outputs a high signal (i.e., ‘1’) when not expired and a low signal (i.e., ‘0’) when expired).
Regarding claim 17, Sasaki-Noble teach the method of claim 11, wherein the second signal is a low-level signal, and the first signal is a high-level signal (Sasaki - the device number of the operation controlling apparatus 10 is low (“0”) ... the device number of the standby controlling apparatus 20 is high (“1”))([0036] and [0037]).
Response to Arguments
Applicant's arguments, see page 5 of applicant's remarks, filed April 1, 2026, with respect to the 35 U.S.C. §112 rejection have been fully considered and are persuasive. The 35 U.S.C. §112 rejection has been withdrawn.
Applicant's arguments, see pages 5-9 of applicant’s remarks, filed April 1, 2026, with respect to the 35 U.S.C. §103 rejection have been fully considered but they are not persuasive.
Regarding claims 1-17, applicant argues the combination of Sasaki-Noble fails to teach “wherein when the first CPLD receives the first control request signal from the first BMC and a first signal from the second CPLD, the first BMC is determined to be a main controller of the multi-host system, and the first CPLD outputs a second signal to the second CPLD”; the examiner respectfully disagrees.
As an exemplary embodiment Noble depicts two controller and two corresponding state control circuits in Figure 4 “FIG. 4 illustrates an exemplary configuration of a system 400 ... As shown, state control circuit 404-1 is associated with controller 402-1 ... State control circuit 404-2 may be similarly associated with controller 402-2” (column 46 lines 16-17 and lines 33-41) such that the state control circuits (i.e., logic devices) communicate with each other (i.e., send and receive signals from one device to another device) using a communication link “As shown, state control circuit 404-1 and state control circuit 404-2 are communicatively coupled to each other via a link 414. Link 414 may be implemented in a variety of ways to allow state control circuit 404-1 and state control circuit 404-2 to communicate with each other. For example, link 414 may be ... wires ... a wireless link ... etc.” (column 46 lines 47-54) and in which each controller periodically (i.e., at preset time intervals) sends a master signal “Each controller may be configured to send periodic request master signals” (column 50 lines 1-2).
In particular, Noble discloses a first controller is determined to be a main controller based on a first logic processor receiving a first control signal from the first controller and a first signal from a second logic processor and wherein the first logic processor outputs a second signal to the second logic processor “FIG. 5 shows an exemplary configuration 500 of state control circuits ... state control circuit 404-1 … Watchdog timer 508-1 ... a timer output 512-1 … Gate 514-1 includes inputs coupled to master input 504-1 and a timer output 512-2 from a watchdog timer 508-2 of state control circuit 404-2 ... state control circuit 404-1 may receive a request master signal from controller 402-1 via master input 504-1. The request master signal may indicate a request for controller 402-1 to operate in the master state ... Gate 514-1 may allow the request master signal to pass through ... to watchdog timer 508-1 based on the timer output signal from watchdog timer 508-2” (column 47 lines 43-52, column 48 lines 28-35).
Specifically, Noble depicts in Figure 5 of a first controller (i.e., controller 402-1) is determined to be a main (i.e., master) controller based on a first logic processor (i.e., state control 404-1) receiving a control signal (i.e., master 504-1) from the first controller and a signal from a second logic processor (i.e., timer output 512-2 from state control 404-2) such that the first logic processor outputs a signal (i.e., timer output 512-1) to the second logic processor. As previously noted a watchdog outputs a high signal (i.e., ‘1’) when not expired and a low signal (i.e., ‘0’) when expired, thus an AND gate with one inverted input will cause the first logic processor to output a second (i.e., high) signal when the control signal is received from the first controller and a first (i.e., low) signal is received from the second logic processor.
Conclusion
The prior art made of record on form PTO-892 and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider the reference fully when responding to this action. The document cited therein and enumerated below teaches a method and apparatus a baseboard management controller.
US12481337B2
US12554568B2
US20240160264A1
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Yongjia Pan whose telephone number is (571)270-1177. The examiner can normally be reached Monday - Friday, 9:00 AM - 5:00 PM EST.
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/YONGJIA PAN/Primary Examiner, Art Unit 2118
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