DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Group II, Species E and sub-species E1 in the reply filed on May 04, 2026 is acknowledged. Applicant elected claims 8-10, 13-14 and 20. However, claim 20 depends upon claim the independent claim 16 which was not elected. Since claims 16 and 17 are generic therefore, these claims along with claim 20 are being examined. Claims 1-7, 11-12, 15, and 18-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 16, the claim recites a carrier substrate having a second dummy mold structure and a second bonding layer and further recites a frontside interconnect structure having a first dummy mold structure and a first bonding layer. However, the claim does not recite the structural relationship between the carrier substrate/second dummy mold structure/second bonding layer and the frontside interconnect structure/first mold structure/first bonding layer. For example, the claim does not specify whether the first and second bonding layers are joined, bonded or otherwise structurally connected to each other. Hence the metes and bounds of the claim are not clear as the claimed method does not clearly define how the carrier substrate and the frontside interconnection structure are to be arranged relative to each other.
Claims 17 and 20 depend upon claim 16 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-10 and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chu et al. (US 2021/0399099 A1; hereafter Chu).
Regarding claim 8, Chu teaches a method for fabricating a semiconductor device (see e.g., Figures 1-16) the method comprising:
providing a semiconductor substrate (see e.g., substrate 20 including a base silicon layer 201, insulation layer 202 and a top silicon layer 203, Para [0015], Figure 2) including a first surface on which an active region is formed (see e.g., the substrate 20 has a first surface on which fin-shaped structures 210 are formed. After the fin-shaped structures 210 are formed, an isolation feature 212 is formed between fin-shaped structures 210 while a portion of the fin-shaped structures 210 rise above the isolation feature, Para [0016], Figure 4) and a second surface opposite the first surface (see e.g., the substrate 20 has a second surface opposite the first surface, Figure 4);
forming an electronic element on the active region (see e.g., nanosheet transistors with gate structure 220, source features 225S and drain features 225D are formed on the first surface of the substrate 20, Paras [0015] – [0017], [0020], Figure 5);
forming a frontside interconnection structure on the first surface of the semiconductor substrate (see e.g., frontside interconnect structure including the second dielectric layer 240 and the metal lines 242 is formed on the first surface of the substrate 20, Para [0021], Figure 5) the frontside interconnection structure being electrically connected to source/drain regions of the electronic element (see e.g., frontside source/drain contact vias maybe formed to electrically couple the source features 225S and the drain features 225D to the frontside interconnection structure, Para [0021]);
forming a first dummy mold structure on the frontside interconnection structure (see e.g., depositing a first oxide layer 244 over the frontside interconnection structure, Para [0021], Figure 5), the first dummy mold structure comprising a first bonding layer (see e.g., the top bonding surface of the first oxide layer 244 is interpreted as the first bonding layer, Figure 6);
providing a carrier substrate including a third surface and a fourth surface, the fourth surface being opposite the third surface (see e.g., a carrier substrate 248, having a third surface and a fourth surface opposite the third surface, Para [0022], Figure 6);
forming a second dummy mold structure on the third surface of the carrier substrate (see e.g. the carrier substrate includes a second oxide layer 246 on its third surface, Para [0022], Figure 6), the second dummy mold structure comprising a second bonding layer (see e.g., the top bonding surface of oxide 246 is interpreted as the second bonding layer, Figure 6); attaching the semiconductor substrate to the carrier substrate by disposing the first bonding layer and the second bonding layer to face each other; and (see e.g., the top surface of the first oxide 244 and the top surface of the second oxide 246 are brought in to contact and bonded together by fusion bonding, Para [0022], Figure 6)
forming a backside interconnection structure on the second surface of the semiconductor substrate (see e.g., buried power rail 266 formed opposite the frontside interconnect structure, Para [0035], Figure 16), the backside interconnection structure being electrically connected to the source/drain regions (see e.g., the buried power rail 266 is electrically connected to the source 225S via a backside metal plug 264, Pars [0035], [0036], Figure 16).
Regarding claim 9, Chu, as referred in claim 8, further teaches
further comprising thinning the second surface of the semiconductor substrate, to reduce a cross-sectional thickness thereof, after forming the front side interconnection structure and before forming the backside interconnection structure (see e.g., once the carrier substrate 248 is bonded to the frontside of the workpiece 200, the workpiece 200 is flipped over the substrate 20 is pointed upwards such that the base silicon layer 201 is disposed over the insulation layer 202. Next a portion of the substrate is removed that is the base silicon layer 201 and the insulation layer 202 are removed by a grinding process or a planarization process, such as a CMP process until the isolation feature 212 and the top silicon layer 203 are planar. A buried power rail 266 is then formed on the backside of the substrate, Paras [0022], [0023], Figures 7-16).
Regarding claim 10, Chu, as referred in claim 8 further teaches
wherein the first bonding layer includes the same material as that of the first dummy mold structure, and (see e.g., the top surface of the first oxide layer is interpreted as the first bonding layer. Accordingly, because the first bonding layer is part of the first oxide layer, the first bonding layer is considered to comprise the same material as the first oxide layer, Figure 6)
the second bonding layer includes the same material as that of the second dummy mold structure (see e.g., the top surface of the second oxide layer is interpreted as the second bonding layer. Accordingly, because the second bonding layer is part of the second oxide layer, the second bonding layer is considered to comprise the same material as the second oxide layer, Figure 6).
Regarding claim 16, Chu teaches a method for fabricating a semiconductor device (see e.g., Figures 1-16), the method comprising:
providing a semiconductor substrate (see e.g., substrate 20 including a base silicon layer 201, insulation layer 202 and a top silicon layer 203, Para [0015], Figure 2) including an active region defined by an element isolation trench and including a first surface and a second surface, the second surface being opposite the first surface (see e.g., the substrate 20 has a first surface on which fin-shaped structures 210 are formed. After the fin-shaped structures 210 are formed, an isolation feature 212 is formed between fin-shaped structures 210 while a portion of the fin-shaped structures 210 rise above the isolation feature. The substrate 20 has a second surface opposite the first surface, Para [0016], Figure 4);
forming an electronic element including an active pattern on the active region and extending in a first direction parallel to an upper surface of the semiconductor substrate, a gate structure extending in a second direction intersecting the first direction and parallel to the upper surface of the semiconductor substrate, and source/drain regions on sides of the gate structure (see e.g., nanosheet transistors with gate structure 220, source features 225S and drain features 225D on the sides of the gate structure, extend from and are formed on the first surface of the substrate 20, Paras [0015] – [0017], [0020], Figures 2-5);
forming a frontside interconnection structure on the first surface of the semiconductor substrate (see e.g., frontside interconnect structure including the second dielectric layer 240 and the metal lines 242 is formed on the first surface of the substrate 20, Para [0021], Figure 5), the frontside interconnection structure comprising a power line electrically connected to the source/drain regions (see e.g., the frontside source contact 280 is coupled to a frontside power rail in the frontside interconnect structure by way of a frontside silicide layer 282. The source feature 225S in the semiconductor device 200 is coupled to the frontside power rail, Para [0036], Figure 16);
forming a first dummy mold structure on the frontside interconnection structure (see e.g., depositing a first oxide layer 244 over the frontside interconnection structure, Para [0021], Figure 5), the first dummy mold structure comprising a first bonding layer (see e.g., the top bonding surface of the first oxide layer 244 is interpreted as the first bonding layer, Figure 6);
providing a carrier substrate including a third surface and a fourth surface, the fourth surface being opposite the third surface; and (see e.g., a carrier substrate 248, having a third surface and a fourth surface opposite the third surface, Para [0022], Figure 6)
forming a second dummy mold structure on the third surface of the carrier substrate (see e.g. the carrier substrate includes a second oxide layer 246 on its third surface, Para [0022], Figure 6), the second dummy mold structure comprising a second bonding layer (see e.g., the top bonding surface of oxide 246 is interpreted as the second bonding layer, Figure 6),
wherein the first dummy mold structure is between the frontside interconnection structure and the first bonding layer, and (see e.g., first oxide layer 244 is positioned between the frontside interconnection structure and the top bonding surface of oxide 244 interpreted as the first bonding layer, Figure 6)
the second dummy mold structure is between the third surface of the carrier substrate and the second bonding layer (see e.g., second oxide layer 246 is positioned between the carrier substrate 248 and the top bonding surface of oxide 246 interpreted as the second bonding layer, Figure 6).
Regarding claim 17, Chu, as referred in claim 16, further teaches
further comprising forming a backside interconnection structure on the second surface of the semiconductor substrate (see e.g., buried power rail 266 formed opposite the frontside interconnect structure, Para [0035], Figure 16), the backside interconnection structure being connected to the source/drain regions (see e.g., the buried power rail 266 is electrically connected to the source 225S via a backside metal plug 264, Pars [0035], [0036], Figure 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 2021/0399099 A1; hereafter Chu) in view of Shih et al. (US 2023/0317674 A1; hereafter Shih).
Regarding claim 13, Chu, as referred in claim 8, does not explicitly teach
“wherein the first dummy mold structure includes a first dummy mold layer and a second dummy mold layer, which are sequentially stacked in a vertical direction between the frontside interconnection structure and the first bonding layer,
the second dummy mold structure includes a third dummy mold layer and a fourth dummy mold layer, which are sequentially stacked in the vertical direction between the third surface of the carrier substrate and the second bonding layer,
the first dummy mold layer and the second dummy mold layer include different materials, and
the third dummy mold layer and the fourth dummy mold layer include different materials”.
In a similar field of endeavor Shih teaches
wherein the first dummy mold structure includes a first dummy mold layer and a second dummy mold layer, which are sequentially stacked in a vertical direction between the frontside interconnection structure and the first bonding layer (see e.g., second dielectric layer 113 is positioned between the frontside interconnect structure 108 and the bonding layer 104. The second dielectric layer 113 may include one or more dielectric materials such as, SiO.sub.2, SiN, SiON, SiCN, SiOCN., Para [0076], Figure 4D),
Thus, Shih suggests that the dielectric structure between the frontside interconnect structure 108 and the bonding layer 104 may be formed as a multilayer dielectric structure including different dielectric materials.
the second dummy mold structure includes a third dummy mold layer and a fourth dummy mold layer, which are sequentially stacked in the vertical direction between the third surface of the carrier substrate and the second bonding layer (see e.g., first dielectric layer 112 is positioned between the carrier substrate 102 and the bonding layer 104. The first dielectric layer 112 may include one or more dielectric materials such as, SiO.sub.2, SiN, SiON, SiCN, SiOCN, Para [0033], Figure 4D),
Thus, Shih suggests that the dielectric structure between the carrier substrate 102 and the bonding layer 104 may be formed as a multilayer dielectric structure including different materials.
the first dummy mold layer and the second dummy mold layer include different materials, and
the third dummy mold layer and the fourth dummy mold layer include different materials.
Shih teaches that each of the first dielectric layer 112 and a second dielectric layer 113 may include one or more dielectric materials such as, SiO.sub.2, SiN, SiON, SiCN, SiOCN. Accordingly, when first dielectric layer 112 and the second dielectric layer 113 are each formed as multilayer structures, the respective layers maybe formed of different dielectric materials selected from the disclosed materials. Thus, Shih teaches the first and second dummy mold layers being made of different materials and likewise teaches the third and furth dummy mold layers being made of different materials.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of wherein the first dummy mold structure includes a first dummy mold layer and a second dummy mold layer, which are sequentially stacked in a vertical direction between the frontside interconnection structure and the first bonding layer,
the second dummy mold structure includes a third dummy mold layer and a fourth dummy mold layer, which are sequentially stacked in the vertical direction between the third surface of the carrier substrate and the second bonding layer,
the first dummy mold layer and the second dummy mold layer include different materials, and
the third dummy mold layer and the fourth dummy mold layer include different materials in the method of Chu in order to improve bonding reliability between the semiconductor substrate and the carrier substrate, protect the frontside interconnection structure during subsequent backside processing and improve mechanical support.
Regarding claim 14, Chu, as modified by Shih, teaches the limitations of claim 13 as mentioned above. Chu does not explicitly teach
“wherein the first dummy mold layer and the fourth dummy mold layer include the same material, and the second dummy mold layer and the third dummy mold layer include the same material”.
In a similar field of endeavor Shih teaches
wherein the first dummy mold layer and the fourth dummy mold layer include the same material, and the second dummy mold layer and the third dummy mold layer include the same material.
Shih teaches the dielectric structures 112 and 113 may include one or more dielectric materials such as, SiO.sub.2, SiN, SiON, SiCN, SiOCN. Although Shih does not require any particular arrangement of the listed dielectric materials, it would have been obvious to one skilled in the art to select corresponding materials from Shih’s disclosed group such that the first and fourth dummy mold layers include the same material, and the second and third dummy mold layers include the same materials. Such a selection would have been a predictable design choice to improve bonding compatibility and reliability.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of wherein the first dummy mold layer and the fourth dummy mold layer include the same material, and the second dummy mold layer and the third dummy mold layer include the same material in order to improve bonding performance.
Regarding claim 20, Chu, as referred in claim 16, does not explicitly teach
“wherein the first dummy mold structure includes a first dummy mold layer and a second dummy mold layer which are sequentially stacked, in a third direction perpendicular to the first and second directions, between the frontside interconnection structure and the first bonding layer, and
the second dummy mold structure includes a third dummy mold layer and a fourth dummy mold layer which are sequentially stacked in the third direction between the third surface of the carrier substrate and the second bonding layer”.
In a similar field of endeavor Shih teaches
wherein the first dummy mold structure includes a first dummy mold layer and a second dummy mold layer which are sequentially stacked, in a third direction perpendicular to the first and second directions, between the frontside interconnection structure and the first bonding layer, and (see e.g., second dielectric layer 113 is positioned between the frontside interconnect structure 108 and the bonding layer 104. The second dielectric layer 113 may include one or more dielectric materials such as, SiO.sub.2, SiN, SiON, SiCN, SiOCN., Para [0076], Figure 4D)
Thus, Shih suggests that the dielectric structure between the frontside interconnect structure 108 and the bonding layer 104 may be formed as a multilayer dielectric structure including different dielectric materials.
the second dummy mold structure includes a third dummy mold layer and a fourth dummy mold layer which are sequentially stacked in the third direction between the third surface of the carrier substrate and the second bonding layer (see e.g., first dielectric layer 112 is positioned between the carrier substrate 102 and the bonding layer 104. The first dielectric layer 112 may include one or more dielectric materials such as, SiO.sub.2, SiN, SiON, SiCN, SiOCN, Para [0033], Figure 4D)
Thus, Shih suggests that the dielectric structure between the carrier substrate 102 and the bonding layer 104 may be formed as a multilayer dielectric structure including different materials.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of wherein the first dummy mold structure includes a first dummy mold layer and a second dummy mold layer which are sequentially stacked, in a third direction perpendicular to the first and second directions, between the frontside interconnection structure and the first bonding layer, and
the second dummy mold structure includes a third dummy mold layer and a fourth dummy mold layer which are sequentially stacked in the third direction between the third surface of the carrier substrate and the second bonding layer in the method of Chu to improve bonding reliability between the semiconductor substrate and the carrier substrate, protect the frontside interconnection structure during subsequent backside processing and improve mechanical support.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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