Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1-4,7-8,18 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20200365491 A1 (Kawashima).
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Regarding claim 1, Kawashima shows (Fig. 3) a power semiconductor module comprising:
a first substrate (18, para 62);
a second substrate (16, para 62) formed over the first substrate;
a conductive member (20, para 62) disposed between the first substrate and the second substrate;
a first semiconductor device (14, para 62) disposed between the first substrate and the conductive member; and
a second semiconductor device (12, para 62) disposed between the conductive member and the second substrate, wherein the conductive member is electrically connected to the first power semiconductor device and the second power semiconductor device (para 6).
Regarding claim 2, Kawashima shows (Fig. 3) wherein the first semiconductor device (14, para 62) and the second semiconductor device (12, para 62) at least partially overlap.
Regarding claim 3, Kawashima shows (Fig. 3) wherein the first semiconductor device (14, para 62) and the second semiconductor device (12, para 62) are electrically connected in series (as drain (12c) of 12 is connected to source (14b) of 14).
Regarding claim 4, Kawashima shows (Fig. 3) wherein the conductive member comprises:
one part (20, para 62); and a connection part (34, para 71) connected to said one part, and the second semiconductor device (12) is disposed on a surface of said one part.
Regarding claim 7, Kawashima shows (Fig. 3) further comprising a spacer (15, para 69) disposed between the first semiconductor device (14) and the conductive member (20).
Regarding claim 8, Kawashima shows (Fig. 3) wherein the spacer (15) extends from the conductive member (20) toward the first semiconductor device (14).
Regarding claim 18, Kawashima shows (Fig. 3) wherein a current path is configured to be formed through the first substrate (18), the first semiconductor device (14), the conductive member (20), the second semiconductor device (12), and the second substrate (16) in a sequence of the first substrate, the first semiconductor device, the conductive member, the second semiconductor device, and the second substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 15-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima in view of US 20240290757 A1 (Prajuckamol).
Regarding claim 15, Kawashima shows first semiconductor device, the first substrate and the conductive member.
Kawashima does not show a plurality of first semiconductor devices including the first semiconductor device, wherein the plurality of first semiconductor devices are connected in parallel between the first substrate and the conductive member.
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Prajuckamol shows (Fig. 1) a plurality of first semiconductor devices (141, para 28) including the first semiconductor device (MOSFET, para 31), wherein the plurality of first semiconductor devices are connected in parallel between the first substrate (120, para 27) and the conductive member (130, para 28).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Prajuckamol, with plurality of first semiconductor devices, to the invention of Kawashima.
The motivation to do so is that the combination produces the predictable result of improved current carrying capability (para 31).
Regarding claim 16, Prajuckamol shows (Fig. 1) a plurality of second semiconductor devices (140, para 28) including the second semiconductor device, wherein the plurality of second semiconductor devices are connected in parallel between the conductive member and the second substrate (110, para 27).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Prajuckamol, with plurality of first semiconductor devices, to the invention of Kawashima.
The motivation to do so is that the combination produces the predictable result of improved current carrying capability of second semiconductor devices (para 31).
Regarding claim 17, Prajuckamol shows (Fig. 1) wherein each of the plurality of first power semiconductor devices (141, para 28) and each of the plurality of second power semiconductor devices (140, para 28) at least partially overlap.
Regarding claim 19, Kawashima shows (Fig. 3) a power converter (10, para 61), comprising:
a power semiconductor module comprises:
a first substrate (18, para 62);
a second substrate (16, para 62) on the first substrate;
a conductive support (20, para 62) having a plate shape and between the first substrate and the second substrate;
a first power semiconductor device (14, para 62) between the first substrate and the conductive support; and
a second power semiconductor device (12, para 62) between the conductive support and the second substrate, wherein the conductive support is configured to be connected in surface contact with an upper surface of the first power semiconductor device and connected in surface contact with a lower surface of the second power semiconductor device.
Kawashima does not show the power converter having a plurality of power semiconductor modules.
Prajuckamol shows (Fig. 1) the power converter having a plurality of power semiconductor modules (para 21-22).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Prajuckamol, with plurality of power semiconductor modules, to the invention of Kawashima.
The motivation to do so is that the combination produces the predictable result of forming a power conversion device (para 22).
2. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima in view of Prajuckamol as applied to claim 19 above, further in view of US 20240387474 A1 (Nakamura).
Regarding claim 20, Kawashima in view of Prajuckamol shows the power semiconductor module, the first power semiconductor device and the second power semiconductor device.
Kawashima in view of Prajuckamol does not show an inverter comprising a plurality of legs, wherein each of the plurality of legs comprises the power semiconductor module, and wherein each of the plurality of legs comprises: a first arm comprising the first power semiconductor device; and a second arm comprising the second power semiconductor device.
Nakamura shows (Fig. 1) an inverter (6, para 150) comprising a plurality of legs, wherein each of the plurality of legs (9, para 151) comprises the power semiconductor module, and wherein each of the plurality of legs comprises: a first arm (upper MOSFET 11 and diode 12) comprising the first power semiconductor device (upper MOSFET 11); and a second arm (lower MOSFET 11 and diode 12) comprising the second power semiconductor device (lower MOSFET 11).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Nakamura, with plurality of legs, to the invention of Kawashima in view of Prajuckamol.
The motivation to do so is that the selection of an art recognized inverter of Prajuckamol is suitable for the intended use of Kawashima in view of Prajuckamol (MPEP §2144.07).
Allowable Subject Matter
Claims 5-6, 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the connection part, and said one part, and the first semiconductor device is disposed within the recess”.
Regarding claim 9, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the first gate electrode is electrically connected to the first substrate using a wire”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812