Prosecution Insights
Last updated: October 01, 2026
Application No. 18/530,849

MICRO-LED DBR FABRICATION BY ELECTROCHEMICAL ETCHING

Final Rejection §103
Filed
Dec 06, 2023
Priority
Jan 17, 2023 — provisional 63/480,243
Examiner
HRNJIC, ADIN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Snap Inc.
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
39 granted / 59 resolved
-1.9% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
28 currently pending
Career history
105
Total Applications
across all art units

Statute-Specific Performance

§103
56.6%
+16.6% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 59 resolved cases

Office Action

§103
Detailed Action This office action is in response to the amendment filed on June 23rd, 2026. Claims 1-6, 8-19, and 21-22 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed June 23rd, 2026, have been fully considered but they are not persuasive. Applicant argues (pgs. 10-12, “Remarks”) that the combination of Feezell and Huang does not teach the limitations presented in amended Claim 19. Specifically, the do not tach “the dielectric layer extending laterally between the plurality of LED apertures”. While the examiner agrees that the dielectric layer of Feezell does not extend entirely between the apertures, there is a portion of the SiO2 dielectric layer that extends laterally as seen in fig. 4H and exists in the region between the LED apertures. Therefore, applicant’s arguments are not persuasive. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Feezell et al. (2021/0273412 A1; hereinafter Feezell) in view of Huang et al. (2024/0222552 A1; hereinafter Huang). Regarding Claim 19, Feezell (figs. 4A-L) teaches a semiconductor device ([0035], VCSEL) comprising: a distributed Bragg reflector (DBR) ([0036], NP-DBR) comprising a plurality of pairs of alternating adjacent layers ([0035], alternating layers of UID-GaN and N+GaN), each pair of alternating adjacent layers comprising: a silicon doped layer comprising gallium nitride (GaN) and silicon (Si) ([0035], N+GaN with Si-doping); and an un-doped layer comprising gallium nitride (GaN) ([0035], unintentionally doped GaN) and having a lower silicon content than the silicon doped layer (the unintentionally doped GaN is not listed as having a silicon concentration compared to the highly doped N+GaN at a silicon concentration of 1x1019 cm-3); an n-GaN layer ([0036], N-GaN) positioned above the DBR (NP-DBR); a dielectric layer ([0036], SiO2, see fig. 4E) positioned above the n-GaN layer (N-GaN), defining a plurality of LED apertures (LED aperture, see annotated fig. 4H) each extending between an upper surface (upper surface, see annotated fig. 4H) and a lower surface (lower surface, see annotated fig. 4H) of the dielectric layer (SiO2), the dielectric layer (SiO2) extending laterally between the plurality of LED apertures (LED aperture); and positioned within each LED aperture (LED aperture): a micro light emitting diode (microLED) ([0035]-[0036], six-pair InGaN/GaN active region creating multiple quantum wells, or MQW) comprising a superlattice structure comprising a plurality of quantum well layers ([0035]-[0036], six-pair InGaN/GaN active region creating multiple quantum wells), thereby defining a plurality of microLEDs (MQW) of the semiconductor device (VCSEL); a p-GaN layer ([0036], P-GaN) positioned above the microLED (MQW); and a conductive mirror positioned above the p-GaN layer, wherein: at least one aperture ([0036], trench formed after mesa 1, mesa 2, and trench mesa are etched, see figs. 4B, 4D, and 4F) is defined through the plurality of pairs of alternating adjacent layers (trench mesa exposes the entire thickness of NP-DBR, see fig. 4F), the n-GaN layer (N-GaN), and the dielectric layer (SiO2); and at least one silicon doped layer of the DBR (NP-DBR) comprises a nanoporous structure ([0037], selectively porosify the highly doped N+GaN and form nanoporous DBRs). Feezell doesn’t teach a conductive mirror positioned above the p-GaN layer. However, Huang (fig. 1) teaches a conductive mirror ([0035], 150 may be a DBR of metals) positioned above the p-GaN layer ([0033], P-GaN). Huang also teaches an upper DBR made of metal with high reflectivity helps increase the brightness of the light output ([0078]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Feezell to include the conductive mirror of Huang to increase the brightness of the light output. PNG media_image1.png 264 419 media_image1.png Greyscale Annotated Figure 4H Claims 21-22 rejected under 35 U.S.C. 103 as being unpatentable over Feezell and Huang as applied to Claim 19 above, and further in view of Lopez Julia et al. (2023/0122492 A1; hereinafter Lopez Julia). Regarding Claim 21, Feezell doesn’t teach the semiconductor device of claim 19, wherein: the plurality of LED apertures comprises a red LED aperture, a green LED aperture, and a blue LED aperture; and the plurality of microLEDs comprises: a red microLED in the red LED aperture; a green microLED in the green LED aperture; and a blue microLED in the blue LED aperture. However, Lopez Julia (fig. 3B) teaches the plurality of LED apertures ([0028], plurality of 300b) comprises a red LED aperture ([0018], [0023], may be red), a green LED aperture ([0018], [0023], may be green), and a blue LED aperture ([0018], [0023], may be blue); and the plurality of microLEDs ([0023], plurality of 302) comprises: a red microLED ([0023], 302 may be tuned to emit red) in the red LED aperture; a green microLED ([0023], 302 may be tuned to emit green) in the green LED aperture; and a blue microLED ([0023], 302 may be tuned to emit blue) in the blue LED aperture. Lopez Julia also teaches there is a higher degree of reflectivity if the microLED emits the color corresponding to the DBR ([0032]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Feezell to include the color emissions of Lopez Julia to increase reflectivity between the DBR and microLED. Regarding Claim 22, Feezell doesn’t teach the semiconductor device of claim 19, wherein: the plurality of DBR layers comprise: a first plurality of DBR layers forming a red-light DBR configured to reflect light at a wavelength of light emitted by the red microLED; a second plurality of DBR layers forming a green-light DBR configured to reflect light at a wavelength of light emitted by the green microLED; and a third plurality of DBR layers forming a blue-light DBR configured to reflect light at a wavelength of light emitted by the blue microLED. However, Lopez Julia (fig. 3B) teaches the plurality of DBR layers ([0028], plurality of 330) comprise: a first plurality of DBR layers forming a red-light DBR ([0032], 330 may be tailored to the wavelength emitted by 302) configured to reflect light at a wavelength of light emitted by the red microLED ([0023], 302 may be tuned to emit red); a second plurality of DBR layers forming a green-light DBR ([0032], 330 may be tailored to the wavelength emitted by 302) configured to reflect light at a wavelength of light emitted by the green microLED ([0023], 302 may be tuned to emit green); and a third plurality of DBR layers forming a blue-light DBR ([0032], 330 may be tailored to the wavelength emitted by 302) configured to reflect light at a wavelength of light emitted by the blue microLED ([0023], 302 may be tuned to emit blue). Lopez Julia also teaches there is a higher degree of reflectivity if the microLED emits the color corresponding to the DBR ([0032]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Feezell to include the color emissions of Lopez Julia to increase reflectivity between the DBR and microLED. Allowable Subject Matter Claims 1-6 and 8-18 are allowed. The following is an examiner’s statement of reasons for allowance. None of the cited references, either singly or in combination, teach or render obvious the limitations presented in Claim 1 wherein “after depositing the plurality of DBR layers: forming an n-GaN layer above the DBR; forming a dielectric layer above the n-GaN layer; forming at least one light emitting diode (LED) aperture extending between an upper surface and a lower surface of the dielectric layer; and depositing, into the at least one LED aperture: at least one microLED comprising a superlattice structure comprising a plurality of quantum well layers; and at least one p-GaN layer above the at least one microLED; after depositing the at least one p-GaN layer above the at least one microLED, forming at least one aperture extending through the plurality of DBR layers to expose each DBR layer”. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Martin (2019/0123033 A1) teaches a microLED with color specific DBR layers. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.H./Examiner, Art Unit 2817 /ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 06, 2023
Application Filed
Mar 26, 2026
Non-Final Rejection mailed — §103
May 19, 2026
Interview Requested
Jun 10, 2026
Examiner Interview Summary
Jun 10, 2026
Applicant Interview (Telephonic)
Jun 23, 2026
Response Filed
Sep 16, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
76%
With Interview (+9.7%)
3y 4m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 59 resolved cases by this examiner. Grant probability derived from career allowance rate.

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