Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on March 14th, 2024 and August, 23rd, 2025 were filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feezell et al. (2021/0273412 A1; hereinafter Feezell).
Regarding Claim 1, Feezell (figs. 4A-L) teaches a method of fabricating a semiconductor device ([0035], VCSEL) having a distributed Bragg reflector (DBR) ([0036], NP-DBR), comprising:
depositing, above a DBR deposition surface ([0036], template), a plurality of DBR layers ([0035], alternating layers of UID-GaN and N+GaN) to form a DBR (NP-DBR);
forming at least one aperture ([0036], trench formed after mesa 1, mesa 2, and trench mesa are etched, see figs. 4B, 4D, and 4F) extending through the plurality of DBR layers to expose each DBR layer (trench mesa exposes the entire thickness of NP-DBR, see fig. 4F); and
applying electrochemical etching ([0036], electrochemical porosification, see fig. 4G) to the plurality of DBR layers ([0037], selectively porosify the highly doped N+GaN) via the at least one aperture ([0037], EC etched after deep trenches are formed), thereby transforming at least one DBR layer of the plurality of DBR layers into a nanoporous structure ([0037], selectively porosify the highly doped N+GaN and form nanoporous DBRs).
Regarding Claim 2, Feezell (figs. 4A-L) teaches the method of claim 1, wherein: the plurality of DBR layers comprises a plurality of pairs of alternating adjacent layers ([0035], alternating layers of UID-GaN and N+GaN), each pair of alternating adjacent layers comprising: a silicon doped layer comprising gallium nitride (GaN) and silicon (Si) ([0035], N+GaN with Si-doping); and an un-doped layer comprising gallium nitride (GaN) ([0035], unintentionally doped GaN) and having a lower silicon content than the silicon doped layer (the unintentionally doped GaN is not listed as having a silicon concentration compared to the highly doped N+GaN at a silicon concentration of 1x1019 cm-3); and transforming the at least one DBR layer of the plurality of DBR layers into a nanoporous structure comprises: transforming at least one silicon doped layer of the plurality of DBR layers into a nanoporous structure ([0037], selectively porosify the highly doped N+GaN and form nanoporous DBRs).
Regarding Claim 4, Feezell (figs. 4A-L) teaches the method of claim 1, wherein: forming the at least one aperture comprises dry etching at least one hole through the plurality of DBR layers ([0037], mesa 1, mesa 2, and deep trenches are formed through ICP etching).
Regarding Claim 19, Feezell (figs. 4A-L) teaches a semiconductor device ([0035], VCSEL) comprising:
a distributed Bragg reflector (DBR) ([0036], NP-DBR) comprising a plurality of pairs of alternating adjacent layers ([0035], alternating layers of UID-GaN and N+GaN), each pair of alternating adjacent layers comprising:
a silicon doped layer comprising gallium nitride (GaN) and silicon (Si) ([0035], N+GaN with Si-doping); and
an un-doped layer comprising gallium nitride (GaN) ([0035], unintentionally doped GaN) and having a lower silicon content than the silicon doped layer (the unintentionally doped GaN is not listed as having a silicon concentration compared to the highly doped N+GaN at a silicon concentration of 1x1019 cm-3); wherein:
the DBR (NP-DBR) defines at least one aperture ([0036], trench formed after mesa 1, mesa 2, and trench mesa are etched, see figs. 4B, 4D, and 4F) extending through the plurality of pairs of alternating adjacent layers (trench mesa exposes the entire thickness of NP-DBR, see fig. 4F); and
at least one silicon doped layer of the DBR comprises a nanoporous structure ([0037], selectively porosify the highly doped N+GaN and form nanoporous DBRs).
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Annotated Figure 4H
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Feezell as applied to Claim 2 above, and further in view of Avramescu et al. (2011/0051771 A1; hereinafter Avramescu).
Regarding Claim 3, Feezell (figs. 4A-L) teaches the method of claim 2, wherein at least one silicon doped layer of the plurality of DBR layers further comprises aluminum ([0029], DBR layers may instead be AlGaN) at a concentration greater than 0% and less than 5%.
However, Avramescu teaches the plurality of DBR layers ([0023], alternating layers of DBR) further comprises aluminum at a concentration greater than 0% and less than 5% ([0023], Al ranges from 1% to 5%). Avramescu also teaches that the same or higher reflectivity can be achieved with a lower number of layers reducing cost ([0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Feezell to include aluminum concentration of Avramescu to reduce cost.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Feezell as applied to Claim 1 above, and further in view of Han et al. (2017/0237234 A1; hereinafter Han)
Regarding Claim 5, Feezell doesn’t teach the method of claim 1, wherein: the electrochemical etching is applied using nitric acid (HNO3) between 0.3M and 15.8M and current bias between 3.5V and 10V at a temperature between 0 C and 60 C. Feezell does teach that pore sizes can be controlled through process parameters such as voltage and etchant solution.
However, Han (fig. 5D) teaches the electrochemical etching is applied using nitric acid (HNO3) ([0062], nitric acid for electrochemical etch) between 0.3M and 15.8M ([0047], [0069], approximately 16.7, wherein approximately encompasses +/- 20%) and current bias between 3.5V and 10V ([0047], [0069], approximately 3V, wherein approximately encompasses +/- 20%) at a temperature between 0 C and 60 C ([0062], etching performed at room temperature). Han also teaches that the highly concentrated nitric acid applied at these voltages and temperatures provide improved results and strongly influence pore morphology ([0046]-[0048]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Feezell to include the porosification conditions of Han to provide improved results and influence pore morphology.
Regarding Claim 6, Feezell doesn’t teach the method of claim 1, wherein: the DBR deposition surface comprises a GaN buffer layer; and the method further comprises depositing the GaN buffer layer above a substrate.
However, Han (fig. 5A) teaches the DBR deposition surface comprises a GaN buffer layer ([0052], 510); and the method further comprises depositing the GaN buffer layer (510) above a substrate ([0052], 505). Han also teaches that the buffer layer helps relieve stress and reduce defects that arise from lattice mismatches ([0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Feezell to include the buffer layer of Han to help relieve lattice mismatch stress and defects.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Feezell as applied to Claim 2 above, and further in view of Zhu et al. (2020/0227255 A1; hereinafter Zhu).
Regarding Claim 12, Feezell doesn’t explicitly teach the method of claim 2, wherein: each pair of alternating adjacent layers of the DBR is characterized by a ratio between a thickness of the silicon doped layer and a thickness of the un- doped layer; and the ratios of the pairs of alternating adjacent layers are configured to determine a center wavelength of a stopband of the DBR.
However, Zhu (fig. 2A) teaches each pair of alternating adjacent layers of the DBR ([0169], NID-GaN and N+GaN) is characterized by a ratio between a thickness ([0112], controlling thickness of the layers) of the silicon doped layer (N+GaN) and a thickness of the un- doped layer (NID-GaN); and the ratios of the pairs of alternating adjacent layers are configured to determine a center wavelength of a stopband of the DBR ([0112], controlling thicknesses of the layers may tune the stopband of the DBR). Zhu also teaches that controlling the thickness and tuning the stopband of the DBR may then reflect a desired wavelength of light ([0112]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Feezell to include the thickness control of Zhu to reflect a desired wavelength of light.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Feezell as applied to Claim 19 above, and further in view of Huang et al. (2024/0222552 A1; hereinafter Huang).
Regarding Claim 20, Feezell (figs. 4A-L) teaches the semiconductor device of claim 19, further comprising: an n-GaN layer ([0036], N-GaN) positioned above the DBR (NP-DBR); a dielectric layer ([0036], SiO2, see figs. 4E) positioned above the n-GaN layer, defining at least one LED aperture (LED aperture, see annotated fig. 4H) extending between an upper surface (upper surface, see annotated fig. 4H) and a lower surface (lower surface, see annotated fig. 4H) of the dielectric layer (SiO2); at least one micro light emitting diode (microLED) ([0035]-[0036], six-pair InGaN/GaN active region creating multiple quantum wells, or MQW) positioned within the respective at least one LED aperture (LED aperature), each microLED comprising a superlattice structure comprising a plurality of quantum well layers ([0035]-[0036], six-pair InGaN/GaN active region creating multiple quantum wells); at least one p-GaN layer ([0036], P-GaN) positioned above the respective at least one microLED (MQW); and at least one conductive mirror positioned above the respective at least one p-GaN layer, wherein: the at least one aperture ([0036], trench formed after mesa 1, mesa 2, and trench mesa are etched, see figs. 4B, 4D, and 4F) extends through the plurality of pairs of alternating adjacent layers ([0036]-[0037], trench mesa exposes the entire thickness of NP-DBR, see fig. 4F), the n-GaN layer ([0036]-[0037], mesa 1 etches through the N-GaN layer, see fig. 4B), and the dielectric layer ([0036]-[0037], trench mesa etches through the SiO2 layer, see fig. 4F). Feezell doesn’t teach at least one conductive mirror positioned above the respective at least one p-GaN layer.
However, Huang (fig. 1) teaches at least one conductive mirror ([0035], 150 may be a DBR of metals) positioned above the respective at least one p-GaN layer ([0033], P-GaN). Huang teaches an upper DBR made of a metal with high reflectivity helps increase the brightness of the light output ([0078).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Feezell to include the conductive mirror of Huang to increase the brightness of the light output.
Allowable Subject Matter
Claims 7-11 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. None of the cited references, either singly or in combination, teach or render obvious the limitations presented by Claim 7 wherein “after depositing the plurality of DBR layers and before forming the at least one aperture: forming an n-GaN layer above the DBR; forming a dielectric layer above the n-GaN layer; forming at least one light emitting diode (LED) aperture extending between an upper surface and a lower surface of the dielectric layer; and depositing, into the at least one LED aperture: at least one microLED comprising a superlattice structure comprising a plurality of quantum well layers and at least one p-GaN layer above the at least one microLED”.
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 24, 2026