DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 8 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Di (US 2021/0366875).
Regarding claim 1, Di discloses, in at least figures 1-18 and related text, a semiconductor device assembly, comprising:
a substrate (100, [38]) including a plurality of first electrical contacts (110a (110), [52]);
a plurality of bondable pillars (130, [52]), wherein each bondable pillar, of the plurality of bondable pillars (130, [52]), is coupled to a corresponding first electrical contact, of the plurality of first electrical contacts (110a (110), [52]);
one or more dies (125, [48]) coupled to the substrate (100, [38]) and including a plurality of second electrical contacts (125a/125b, [52]); and
a plurality of wire bonds (134, [52]), wherein each wire bond, of the plurality of wire bonds (134, [52]), bonds a second electrical contact, of the plurality of second electrical contacts (125a/125b, [52]), to a bondable pillar, of the plurality of bondable pillars (130, [52]) (figures).
Regarding claim 4, Di discloses the semiconductor device assembly of claim 1 as described above.
Di further discloses, in at least figures 1-18 and related text, each bondable pillar, of the plurality of bondable pillars (130, [52]), is a copper pillar ([51]).
Regarding claim 8, Di discloses the semiconductor device assembly of claim 1 as described above.
Di further discloses, in at least figures 1-18 and related text, the one or more dies include a die stack including eight or more dies (125, [48]) (figures).
Regarding claim 19, Di discloses, in at least figures 1-18 and related text, a method, comprising:
receiving a substrate (100, [38]) including a plurality of first electrical contacts (110a (110), [52]);
bonding a plurality of bondable pillars (130, [52]) to the substrate (100, [38]), wherein each bondable pillar, of the plurality of bondable pillars (130, [52]), is bonded to a corresponding first electrical contact, of the plurality of first electrical contacts (110a (110), [52]);
coupling one or more dies (125, [48]) to the substrate (100, [38]), the one or more dies (125, [48]) including a plurality of second electrical contacts (125a/125b, [52]); and
bonding the one or more dies (125, [48]) to the plurality of bondable pillars (130, [52]) via a plurality of wire bonds (134, [52]), wherein each wire bond, of the plurality of wire bonds (134, [52]), bonds a second electrical contact, of the plurality of second electrical contacts (125a/125b, [52]), to a bondable pillar, of the plurality of bondable pillars (130, [52]) (figures).
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2020/0075548).
Regarding claim 1, Kim discloses, in at least figure 2A and related text, a semiconductor device assembly, comprising:
a substrate (210-a, [27]) including a plurality of first electrical contacts (bond pad of 210-a, [27]);
a plurality of bondable pillars (240-a through 240-d, [27]), wherein each bondable pillar, of the plurality of bondable pillars (240-a through 240-d, [27]), is coupled to a corresponding first electrical contact, of the plurality of first electrical contacts (bond pad of 210-a, [27]) ([27]);
one or more dies (230-a through 230-d, [26]) coupled to the substrate (210-a, [27]) and including a plurality of second electrical contacts (225, [26]); and
a plurality of wire bonds (250-a through 250-d, [25]), wherein each wire bond, of the plurality of wire bonds (250-a through 250-d, [25]), bonds a second electrical contact, of the plurality of second electrical contacts (225, [26]), to a bondable pillar, of the plurality of bondable pillars (240-a through 240-d, [27]).
Regarding claim 4, Kim discloses the semiconductor device assembly of claim 1 as described above.
Kim further discloses, in at least figure 2A and related text, each bondable pillar, of the plurality of bondable pillars (240-a through 240-d, [27]), is a copper pillar ([28]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Vincent (US 2020/0152579).
Regarding claim 2, Di discloses the semiconductor device assembly of claim 1 as described above.
Di does not explicitly disclose the plurality of first electrical contacts are lead fingers associated with a lead frame associated with the substrate.
Vincent teaches, in at least figures 1-2E and related text, the device comprising the plurality of first electrical contacts (104, [14]) are lead fingers associated with a lead frame (102, [14]) associated with the substrate (101, [14]), for the purpose of providing tiered through mold via (TMV) having a high aspect ratio that is formed through a package body and exposes a ground contact area on the package substrate ([12]) thereby preventing EMI from the packaged device.
Di and Vincent are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di with the specified features of Vincent because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di to have the plurality of first electrical contacts being lead fingers associated with a lead frame associated with the substrate, as taught by Vincent, for the purpose of providing tiered through mold via (TMV) having a high aspect ratio that is formed through a package body and exposes a ground contact area on the package substrate ([12], Vincent) thereby preventing EMI from the packaged device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Chen (US 2014/0061932).
Regarding claim 3, Di discloses the semiconductor device assembly of claim 1 as described above.
Di does not explicitly disclose the plurality of wire bonds includes a plurality of gold wires.
Chen teaches, in at least figure 1 and related text, the device comprising the plurality of wire bonds (154, [11]) includes a plurality of gold wires ([11]), for the purpose of providing increased feature density for ICs which enables more functionality to be integrated into an IC package within a minimized surface area or "footprint" on a PCB ([5]).
Di and Chen are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di to have the plurality of wire bonds including a plurality of gold wires, as taught by Chen, for the purpose of providing increased feature density for ICs which enables more functionality to be integrated into an IC package within a minimized surface area or "footprint" on a PCB ([5], Chen).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Son (US 2016/0315040).
Regarding claim 5, Di discloses the semiconductor device assembly of claim 1 as described above.
Di does not explicitly disclose each bondable pillar, of the plurality of bondable pillars, is coupled to the corresponding first electrical contact, of the plurality of first electrical contacts, via a solder bond.
Son teaches, in at least figures 7, 8A and related text, the device comprising each bondable pillar, of the plurality of bondable pillars (210, [114]), is coupled to the corresponding first electrical contact, of the plurality of first electrical contacts (132, [67]), via a solder bond (120, [73]), for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7]).
Di and Son are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di with the specified features of Son because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di to have the each bondable pillar, of the plurality of bondable pillars, being coupled to the corresponding first electrical contact, of the plurality of first electrical contacts, via a solder bond, as taught by Son, for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7], Son).
Regarding claim 6, Di in view of Son discloses the semiconductor device assembly of claim 5 as described above.
Son further teaches, in at least figures 7, 8A and related text, the solder bond (120, [73]) includes a gold solder material ([73]), for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7]).
Claim(s) 10, 13 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Chen (US 2019/0341366).
Regarding claim 10, Di discloses, in at least figures 1-18 and related text, a memory package, comprising:
a substrate (100, [38]) including a plurality of first electrical contacts (110a (110), [52]);
a plurality of bondable pillars (130, [52]), wherein each bondable pillar, of the plurality of bondable pillars (130, [52]), is coupled to a corresponding first electrical contact, of the plurality of first electrical contacts (110a (110), [52]);
a memory controller (122, [46], [47]) coupled to the substrate (100, [38]);
a memory die stack (stack of 125, [48]) coupled to the substrate (100, [38]) and including a plurality of memory dies (125, [48]) and a plurality of second electrical contacts (125a/125b, [52]); and
a plurality of wire bonds (134, [52]), wherein each wire bond, of the plurality of wire bonds (134, [52]), bonds a second electrical contact, of the plurality of second electrical contacts (125a/125b, [52]), to a bondable pillar, of the plurality of bondable pillars (130, [52]) (figures).
Di does not explicitly disclose a plurality of wire bonds electrically coupling the memory die stack to the memory controller.
Chen teaches, in at least figures 9-11 and related text, the device comprising a plurality of wire bonds (132, [44]) electrically coupling the memory die stack (stack of 124/124t, [40]) to the memory controller (114, [35]), for the purpose of providing second set of wire bonds configured to exert a force on the one or more semiconductor die to hold the one or more semiconductor die down on the substrate ([7]) thereby providing stable surface of the package for subsequent process.
Di and Chen are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di to have the plurality of wire bonds electrically coupling the memory die stack to the memory controller, as taught by Chen, for the purpose of providing second set of wire bonds configured to exert a force on the one or more semiconductor die to hold the one or more semiconductor die down on the substrate ([7], Chen) thereby providing stable surface of the package for subsequent process.
Regarding claim 13, Di in view of Chen discloses the memory package of claim 10 as described above.
Di further discloses, in at least figures 1-18 and related text, each bondable pillar, of the plurality of bondable pillars (130, [52]), is a copper pillar ([51]).
Regarding claim 17, Di in view of Chen discloses the memory package of claim 10 as described above.
Di further discloses, in at least figures 1-18 and related text, the memory die stack (stack of 125, [48]) includes eight or more memory dies (125, [48]) (figures).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Chen (US 2019/0341366), and further in view of Vincent (US 2020/0152579).
Regarding claim 11, Di in view of Chen discloses the memory package of claim 10 as described above.
Di in view of Chen does not explicitly disclose the plurality of first electrical contacts are lead fingers associated with a lead frame associated with the substrate.
Vincent teaches, in at least figures 1-2E and related text, the device comprising the plurality of first electrical contacts (104, [14]) are lead fingers associated with a lead frame (102, [14]) associated with the substrate (101, [14]), for the purpose of providing tiered through mold via (TMV) having a high aspect ratio that is formed through a package body and exposes a ground contact area on the package substrate ([12]) thereby preventing EMI from the packaged device.
Di, Chen, and Vincent are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di in view of Chen with the specified features of Vincent because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di in view of Chen to have the plurality of first electrical contacts being lead fingers associated with a lead frame associated with the substrate, as taught by Vincent, for the purpose of providing tiered through mold via (TMV) having a high aspect ratio that is formed through a package body and exposes a ground contact area on the package substrate ([12], Vincent) thereby preventing EMI from the packaged device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Chen (US 2019/0341366), and further in view of Chen (US 2014/0061932).
Regarding claim 12, Di in view of Chen366 discloses the memory package of claim 10 as described above.
Di in view of Chen366 does not explicitly disclose the plurality of wire bonds includes a plurality of gold wires.
Chen932 teaches, in at least figure 1 and related text, the device comprising the plurality of wire bonds (154, [11]) includes a plurality of gold wires ([11]), for the purpose of providing increased feature density for ICs which enables more functionality to be integrated into an IC package within a minimized surface area or "footprint" on a PCB ([5]).
Di, Chen366, and Chen932 are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di in view of Chen366 with the specified features of Chen932 because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di in view of Chen366 to have the plurality of wire bonds including a plurality of gold wires, as taught by Chen932, for the purpose of providing increased feature density for ICs which enables more functionality to be integrated into an IC package within a minimized surface area or "footprint" on a PCB ([5], Chen932).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Chen (US 2019/0341366), and further in view of Son (US 2016/0315040).
Regarding claim 14, Di in view of Chen discloses the memory package of claim 10 as described above.
Di in view of Chen does not explicitly disclose each bondable pillar, of the plurality of bondable pillars, is coupled to the corresponding first electrical contact, of the plurality of first electrical contacts, via a solder bond.
Son teaches, in at least figures 7, 8A and related text, the device comprising each bondable pillar, of the plurality of bondable pillars (210, [114]), is coupled to the corresponding first electrical contact, of the plurality of first electrical contacts (132, [67]), via a solder bond (120, [73]), for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7]).
Di, Chen, and Son are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di in view of Chen with the specified features of Son because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Di in view of Chen to have the each bondable pillar, of the plurality of bondable pillars, being coupled to the corresponding first electrical contact, of the plurality of first electrical contacts, via a solder bond, as taught by Son, for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7], Son).
Regarding claim 15, Di in view of Chen and Son discloses the memory package of claim 14 as described above.
Son further teaches, in at least figures 7, 8A and related text, the solder bond (120, [73]) includes a gold solder material ([73]), for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7]).
Claim(s) 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 2021/0366875) in view of Son (US 2016/0315040).
Regarding claim 20, Di discloses the method of claim 19 as described above.
Di does not explicitly disclose bonding the plurality of bondable pillars to the substrate includes soldering the plurality of bondable pillars to the plurality of first electrical contacts using a solder paste.
Son teaches, in at least figures 7, 8A and related text, the method comprising bonding the plurality of bondable pillars (210, [114]) to the substrate (134, [64]) includes soldering the plurality of bondable pillars (210, [114]) to the plurality of first electrical contacts (132, [67]) using a solder paste (120, [73]), for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7]).
Di and Son are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Di with the specified features of Son because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Di to have the bonding the plurality of bondable pillars to the substrate includes soldering the plurality of bondable pillars to the plurality of first electrical contacts using a solder paste, as taught by Son, for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7], Son).
Regarding claim 21, Di in view of Son discloses the method of claim 20 as described above.
Di further discloses, in at least figures 1-18 and related text, the bondable pillars (130, [52]) are copper pillars ([51]).
Son further teaches, in at least figures 7, 8A and related text, soldering the plurality of bondable pillars (210, [114]) to the plurality of first electrical contacts (132, [67]) includes soldering the plurality of bondable pillars (210, [114]) to the plurality of first electrical contacts (132, [67]) using a gold solder paste (120, [73]), for the purpose of providing semiconductor package having high bonding strength and a high degree of precision ([7]).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 7 that recite "a distal end of each bondable pillar, of the plurality of bondable pillars, is disposed approximately 30 micrometers below, in the direction, a corresponding second electrical contact, of the plurality of second electrical contacts" in combination with other elements of the base claims 1 and 7.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 9 that recite "a cross-sectional area of each bondable pillar, of the plurality of bondable pillars, is approximately equal to a surface area of each first electrical contact, of the plurality of first electrical contacts" in combination with other elements of the base claims 1 and 9.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 10 and 16 that recite "a distal end of each bondable pillar, of the plurality of bondable pillars, is disposed approximately 30 micrometers below, in the direction, a corresponding second electrical contact, of the plurality of second electrical contacts" in combination with other elements of the base claims 10 and 16.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 10 and 18 that recite "a cross-sectional area of each bondable pillar, of the plurality of bondable pillars, is approximately equal to a surface area of each first electrical contact, of the plurality of first electrical contacts" in combination with other elements of the base claims 10 and 18.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 19 and 22 that recite "bonding the one or more dies to the plurality of bondable pillars via the plurality of wire bonds includes connecting each second electrical contact, of the plurality of second electrical contacts, to a distal end of a corresponding bondable pillar, of the plurality of bondable pillars, that is disposed approximately 30 micrometers below, in a direction, a corresponding second electrical contact" in combination with other elements of the base claims 19 and 22.
Claims 23-25 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 23 that recite "the plurality of bondable pillars is configured to bond to wire bonds electrically coupling the plurality of lead fingers to a corresponding plurality of electrical contacts associated with one or more dies" in combination with other elements of the base claims 23.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811