DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species A of Fig. 4, claims 1-8, 11-14 and 16, in the reply filed on March 27, 2026 is acknowledged. The traversal is on the ground that “… an allowable generic claim may link a reasonable number of species embraced thereby” (page 8, REMARKS). However, this is not found persuasive because the previously identified species A of Fig. 4 and species B of Fig. 5 are directed to distinct and patentably independent structural configurations of a semiconductor assembly. In particular, the semiconductor device assembly 500 drawn to Fig. 5 includes a solder mask formed on the first substrate surface (515) which covers the substrate surface. In contrast, the embodiment of Fig. 4 (species A) does not include such a solder mask feature. Furthermore, the specification expressly discloses the Fig. 5 embodiment as “a more compact version of assembly 400” ([0071]), thereby indicating that the species B represent a different and distinct embodiment with additional structural features. Examiner note that claim 9 is not directed to the elected species A of Fig. 4, because the species A of Fig. 4 does not include a solder mask, and claim 10 depends on claim 9; claims 15 and 17 are directed to the non-elected species B. The requirement is still deemed proper and is therefore made FINAL. Claims 9-10, 15 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b). Therefore, claims 1-8, 11-14 and 16 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over by Yamaguchi (US 2004/0157410) in view of Goldbach et al. (US 2024/0145659, Foreign Priority: Apr. 7, 2021 (DE); hereinafter Goldbach).
Regarding claim 1, Yamaguchi discloses for a semiconductor device assembly, comprising that
a circuit substrate (interposer substrate 51, Fig. 8) comprising a first substrate surface (top surface of 51, Fig. 8), a second substrate surface (bottom surface of 51, Fig. 8) arranged opposite to the first substrate surface (top surface of 51, Fig. 8), a first substrate edge (edge of a left side of 51, Fig. 8) that extend from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8) and a second substrate edge (edge of right side of 51, Fig. 8) that extends from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8) and is arranged opposite to the first substrate edge (edges of left <-> right side of 51, Fig. 8);
a series of holes (a plurality of grooves 54, Fig. 8) arranged along the first substrate edge of the circuit substrate (along left edge of 51, Fig. 8), wherein each hole of the series of holes (54, Fig. 8) extends at least partially from the first substrate surface (top surface of 51, Fig. 8) toward the second substrate surface (bottom surface of 51, Fig. 8);
at least one die (semiconductor substrate 41 including an active region 42, Fig. 8) arranged on the first substrate surface (top surface of 51, Fig. 8); and
Yamaguchi does not explicitly disclose that a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.
However, Goldbach discloses a lead frame 1 (Fig. 4B), which corresponds to the circuit substrate in the claimed invention, includes the depressed edge regions 11K and 12K formed on the left and right edges of the lead frame 1 (Fig. 4B) and since the depressed edge regions 11K and 12K extends at least partially from the top surface to bottom surface of the lead frame 1, therefore, the depressed edge regions 11K and 12K correspond to the series of holes in the claimed invention; Goldbach further discloses the housing body 3 disposed over the lead frame 1, which encapsulates both the top surface of the lead frame 1 and the semiconductor chip 2, which corresponds to the die in the claimed invention; and the housing body 3 fills each of the depressed edge region 11K and 12K (Fig. 4B), therefore, satisfying the claimed limitation that the series of holes are filled.
Since both Yamaguchi and Goldbach teach a semiconductor chip assembly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the housing body of Goldbach into the semiconductor device assembly by Yamaguchi, in order to improve mechanical stability and structural integrity of the overall assembly.
Regarding claim 2, Goldbach further discloses that the package casing (3, Fig. 4B) is mechanically interlocked with the first substrate edge (left edge of 1, Fig. 4B), because “a concave edge region 11K increases the mechanical stability with respect to the adhesion of the housing body 3 to the lead frame 1. Delamination or gap formation between the housing body 3 and the lead frame 1 is made more difficult or prevented by the concave edge region 11K” (emphasis added, [0056]), and as drawn in Fig. 4B, the housing body 3 by Goldbach not only fills the depressed region 11K and 12K, but also extends to the bottom surface of the lead frame, therefore, one ordinary skill in the art would have recognized that the housing body 3 by Goldbach is mechanically interlocked with the lead frame 1.
Regarding claim 3, Yamaguchi further discloses that the first substrate edge (left side of 51, Fig. 8) is a perforated edge formed with the series of holes (Fig. 8).
Regarding claim 4, Yamaguchi further discloses that each hole of the series of holes (54, Fig. 8) defines a respective concaved segment of the first substrate edge (left side of 51, Fig. 8), because the groove 54 on the left side of the interposer substrate 51 has a semicircular concave profile.
Regarding claim 5, Yamaguchi further discloses that each hole of the series of holes (54, Fig. 8) has a perimeter having a substantially semicircular shape (Fig. 8).
Regarding claim 6, Goldbach further discloses that each hole of the series of holes (11K/12K, Fig. 4B) extends partially from the first substrate surface (top surface of 1, Fig. 4B) to the second substrate surface (bottom surface of 1, Fig. 4B).
Regarding claim 7, Goldbach further discloses that a bottom of each hole of the series of holes (bottom portion of 11K/12K, Fig. 4B) is defined by the circuit substrate (1, Fig. 4B), and the package casing (3, Fig. 4B) is in direct contact with the circuit substrate (1, Fig. 4B) at the bottom of each hole of the series of holes (bottom portion of 11K/12K, Fig. 4B).
Regarding claim 8, Yamaguchi further discloses that each hole of the series of holes (a plurality of grooves 54, Fig. 8) extends entirely from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8).
Regarding claim 11, Yamaguchi further discloses that the series of holes (a plurality of 54, Fig. 8) is a first series of holes (54 on the left side of Fig. 8), and
the semiconductor device assembly further comprises:
a second series of holes (54 on the right side of Fig. 8) arranged along the second substrate edge of the circuit substrate (right edge of 54, Fig. 8), wherein each hole (each 54, Fig. 8) of the second series of holes (54 on the right side of Fig. 8) extends at least partially from the first substrate surface (top surface of 54, Fig. 8) toward the second substrate surface (bottom surface of 54, Fig. 8).
Yamaguchi does not explicitly disclose that the package casing fills the second series of holes.
However, Goldbach discloses a lead frame 1 (Fig. 4B), which corresponds to the circuit substrate in the claimed invention, includes the depressed edge regions 11K and 12K formed on the left and right edges of the lead frame 1 (Fig. 4B) and since the depressed edge regions 11K and 12K extends at least partially from the top surface to bottom surface of the lead frame 1, therefore, the depressed edge regions 11K and 12K correspond to the series of holes in the claimed invention; Goldbach further discloses the housing body 3 disposed over the lead frame 1, which encapsulates both the top surface of the lead frame 1 and the semiconductor chip 2, which corresponds to the die in the claimed invention; and the housing body 3 fills each of the depressed edge region 11K and 12K (Fig. 4B), therefore, satisfying the claimed limitation that the series of holes are filled.
Since both Yamaguchi and Goldbach teach a semiconductor chip assembly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the housing body of Goldbach into the semiconductor device assembly by Yamaguchi, in order to improve mechanical stability and structural integrity of the overall assembly.
Regarding claim 12, Goldbach further discloses that the package casing (3, Fig. 4B) is mechanically interlocked with the first substrate edge (left edge of 1, Fig. 4B) and the second substrate edge (right edge of 1, Fig. 4B), because “a concave edge region 11K increases the mechanical stability with respect to the adhesion of the housing body 3 to the lead frame 1. Delamination or gap formation between the housing body 3 and the lead frame 1 is made more difficult or prevented by the concave edge region 11K” (emphasis added, [0056]), and as drawn in Fig. 4B, the housing body 3 by Goldbach not only fills the depressed region 11K and 12K, but also extends to the bottom surface of the lead frame, therefore, one ordinary skill in the art would have recognized that the housing body 3 by Goldbach is mechanically interlocked with the lead frame 1.
Regarding claim 13, Yamaguchi further discloses that the first substrate edge (left edge of 51, Fig. 8) is a first perforated edge (left edge of 51, Fig. 8) formed with the first series of holes (a plurality of grooves 54 on the left side of 51, Fig. 8) and the second substrate edge (right edge of 51, Fig. 8) is a second perforated edge (right edge of 51, Fig. 8) formed with the second series of holes (a plurality of grooves 54 on the right edge of 51, Fig. 8).
Regarding claim 14, Yamaguchi further discloses that each hole (each 54, Fig. 8) of the first series of holes (grooves 54 on the left edge of 51, Fig. 8) and each hole (each 54, Fig. 8) of the second series of holes (grooves 54 on the right edge of 51, Fig. 8) has a perimeter bounded by an arc and a chord of a circle, because the grooves 54 by Yamaguchi has semicircular shape, and therefore, it has a perimeter bounded by an arc and a chord of a circle.
Regarding claim 16, Yamaguchi further discloses for a memory device comprising that a circuit substrate (interposer substrate 51, Fig. 8) comprising a first substrate surface (top surface of 51, Fig. 8), a second substrate surface (bottom surface of 51, Fig. 8) arranged opposite to the first substrate surface (top surface of 51, Fig. 8), a first substrate edge (left edge of 51, Fig. 8) that extends from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8), and a second substrate edge (right edge of 51, Fig. 8) that extends from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8) and is arranged opposite to the first substrate edge (opposite to the left edge of 51, Fig. 8),
wherein a first series of holes (grooves 54 on the left edge of 51, Fig. 8) is arranged along the first substrate edge of the circuit substrate (left edge of 51, Fig. 8) to form a first perforated edge (left edge of 51, Fig. 8),
wherein each hole (each 54, Fig. 8) of the first series of holes (54 on the left edge of 51, Fig. 8) extends at least partially from the first substrate surface (top surface of 51, Fig. 8) toward the second substrate surface (bottom surface of 51, Fig. 8),
wherein a second series of holes (grooves 54 on the right edge of 51, Fig. 8) is arranged along the second substrate edge of the circuit substrate (right edge of 51, Fig. 8) to form a second perforated edge (right edge of 51, Fig. 8),
wherein each hole (each 54, Fig. 8) of the second series of holes (54 on the right edge of 51, Fig. 8) extends at least partially from the first substrate surface (top surface of 51, Fig. 8) toward the second substrate surface (bottom surface of 51, Fig. 8);
at least one memory die (semiconductor substrate 41 including an active region 42, Fig. 8) arranged on the first substrate surface (top surface of 51, Fig. 8).
Yamaguchi does not explicitly disclose that a package molding disposed on the first substrate surface, wherein the package molding encapsulates the at least one memory die and the first substrate surface, and wherein the package molding fills the first series of holes and the second series of holes.
However, Goldbach discloses a lead frame 1 (Fig. 4B), which corresponds to the circuit substrate in the claimed invention, includes the depressed edge regions 11K and 12K formed on the left and right edges of the lead frame 1 (Fig. 4B) and since the depressed edge regions 11K and 12K extends at least partially from the top surface to bottom surface of the lead frame 1, therefore, the depressed edge regions 11K and 12K correspond to the series of holes in the claimed invention; Goldbach further discloses the housing body 3, which corresponds to the package molding in the claimed invention, disposed on the top surface of lead frame 1, which encapsulates both the top surface of the lead frame 1 and the semiconductor chip 2, which corresponds to the at least one memory die in the claimed invention; and the housing body 3 fills each of the depressed edge region 11K and 12K (Fig. 4B); therefore, one of ordinary skill in the art would have recognized that the housing body 3 of Goldbach can be implemented into the semiconductor assembly having a series of holes on the left and right of the substrate by Yamaguchi to fill the holes with the housing body material and to improve structural integrity of the overall assembly.
Since both Yamaguchi and Goldbach teach a semiconductor chip assembly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the housing body of Goldbach into the semiconductor device assembly by Yamaguchi, in order to improve mechanical stability and structural integrity of the overall assembly.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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