DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on June 30, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over by Yamaguchi (US 2004/0157410) in view of Lee et al. (US 2002/0163015, hereinafter Lee).
Regarding claim 1, Yamaguchi discloses for a semiconductor device assembly, comprising that
a circuit substrate (interposer substrate 51, Fig. 8) comprising a first substrate surface (top surface of 51, Fig. 8), a second substrate surface (bottom surface of 51, Fig. 8) arranged opposite to the first substrate surface (top surface of 51, Fig. 8), a first substrate edge (edge of a left side of 51, Fig. 8) that extend from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8) and a second substrate edge (edge of right side of 51, Fig. 8) that extends from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8) and is arranged opposite to the first substrate edge (edges of left <-> right side of 51, Fig. 8);
a series of holes (a plurality of grooves 54, Fig. 8) arranged along the first substrate edge of the circuit substrate (along left edge of 51, Fig. 8), wherein each hole of the series of holes (54, Fig. 8) extends at least partially from the first substrate surface (top surface of 51, Fig. 8) toward the second substrate surface (bottom surface of 51, Fig. 8);
at least one die (semiconductor substrate 41 including an active region 42, Fig. 8) arranged on the first substrate surface (top surface of 51, Fig. 8); and
Yamaguchi does not explicitly disclose that a package casing disposed over the first substrate surface, wherein the package casing is in direct contact with the first substrate edge in each hole of the series of holes and encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.
However, Lee discloses an die paddle 534 including a plurality of marginal recesses 575 formed along edges of the die paddle 534 and extended at least partially from the upper surface toward the lower surface of the die paddle (Fig. 5A-5B), and because Applicants do not specifically claim what material’s composition and/or structural configuration the circuit substrate has, the die paddle 534 and the marginal recesses by Lee correspond to the circuit substrate and series of holes in the claimed invention, respectively. Lee further discloses that the plastic encapsulation (370, Fig. 3A) is disposed over an upper surface of the die paddle (Fig. 3A), therefore, the encapsulation material by Lee corresponds to the package casing in the claimed invention; in view of Fig. 3A in Lee, the encapsulation material is disposed in direct contact with the plurality of marginal recesses 575, encapsulates the semiconductor die (340) and top surface of the die paddle 534, and fills each marginal recess of the plurality of marginal recesses 575 (Fig. 5A). Therefore, Lee teaches a semiconductor assembly through the filled marginal recesses formed along the edge of die paddle, thereby providing a mechanical interlocking structure between the package casing and the circuit substrate, and one of ordinary skill in the semiconductor packaging art would have recognized that such a mechanical interlocking structure improve mechanical stability and/or adhesion between the packaging casing and the substrate.
Since both Yamaguchi and Lee teach a semiconductor chip assembly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the semiconductor packaging having marginal recesses-interlocking mechanism of Lee into the semiconductor device assembly by Yamaguchi, in order to improve mechanical stability and structural integrity of the overall assembly.
Regarding claim 2, Lee further discloses that the package casing (370, Fig. 3A) is mechanically interlocked with the first substrate edge (edge of die paddle, Fig. 5A), because “the die paddle 534 has marginal recesses 575 formed at intervals in and generally perpendicularly to the die paddle margin 572 to reduce stresses and to provide interlock of the die paddle and the encapsulation material” (emphasis added, [0048]), and therefore, one ordinary skill in the art would have recognized that the encapsulation material by Lee is mechanically interlocked with the die paddle.
Regarding claim 3, Yamaguchi further discloses that the first substrate edge (left side of 51, Fig. 8) is a perforated edge formed with the series of holes (Fig. 8).
Regarding claim 4, Yamaguchi further discloses that each hole of the series of holes (54, Fig. 8) defines a respective concaved segment of the first substrate edge (left side of 51, Fig. 8), because the groove 54 on the left side of the interposer substrate 51 has a semicircular concave profile.
Regarding claim 5, Yamaguchi further discloses that each hole of the series of holes (54, Fig. 8) has a perimeter having a substantially semicircular shape (Fig. 8).
Regarding claim 6, Lee further discloses that each hole of the series of holes (575, Fig. 5A) extends partially from the first substrate surface (top surface of 534, Fig. 5B) to the second substrate surface (bottom surface of 534, Fig. 5B).
Regarding claim 7, Lee further discloses that a bottom of each hole of the series of holes (bottom portion of marginal recesses 575, Fig. 5B) is defined by the circuit substrate (534, Fig. 5A-5B), and the package casing (370, Fig. 3A) is in direct contact with the circuit substrate (534, see 334 in Fig. 3B) at the bottom of each hole of the series of holes, because the encapsulation material fills the marginal recesses (Fig. 3A, 8-9).
Regarding claim 8, Yamaguchi further discloses that each hole of the series of holes (a plurality of grooves 54, Fig. 8) extends entirely from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8).
Regarding claim 11, Yamaguchi further discloses that the series of holes (a plurality of 54, Fig. 8) is a first series of holes (54 on the left side of Fig. 8), and
the semiconductor device assembly further comprises:
a second series of holes (54 on the right side of Fig. 8) arranged along the second substrate edge of the circuit substrate (right edge of 54, Fig. 8), wherein each hole (each 54, Fig. 8) of the second series of holes (54 on the right side of Fig. 8) extends at least partially from the first substrate surface (top surface of 54, Fig. 8) toward the second substrate surface (bottom surface of 54, Fig. 8).
Yamaguchi does not explicitly disclose that the package casing fills the second series of holes.
However, Lee discloses the die paddle 534 (Fig. 5A), which corresponds to the circuit substrate in the claimed invention, includes a plurality of marginal recesses 575 at the four edges of the die paddle 534 (Fig. 5A), and when marginal recesses of one of the edges corresponds to the claimed first series holes, marginal recess of another edge can corresponds to the claimed second series of holes; since the encapsulation material encapsulates an entire die paddle (Fig. 3A, 8-9), therefore, all marginal recesses are also filled by the encapsulation material.
Since both Yamaguchi and Lee teach a semiconductor chip assembly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the semiconductor package of Lee into the semiconductor device assembly by Yamaguchi, in order to improve mechanical stability and structural integrity of the overall assembly.
Regarding claim 12, Lee further discloses that the package casing (370, Fig. 3A) is mechanically interlocked with the first substrate edge (one of the edges of 534, Fig. 5A) and the second substrate edge (another edge of 534, Fig. 5A), because “the die paddle 534 has marginal recesses 575 formed at intervals in and generally perpendicularly to the die paddle margin 572 to reduce stresses and to provide interlock of the die paddle and the encapsulation material” (emphasis added, [0048]), and therefore, one ordinary skill in the art would have recognized that the encapsulation material by Lee is mechanically interlocked with the die paddle.
Regarding claim 13, Yamaguchi further discloses that the first substrate edge (left edge of 51, Fig. 8) is a first perforated edge (left edge of 51, Fig. 8) formed with the first series of holes (a plurality of grooves 54 on the left side of 51, Fig. 8) and the second substrate edge (right edge of 51, Fig. 8) is a second perforated edge (right edge of 51, Fig. 8) formed with the second series of holes (a plurality of grooves 54 on the right edge of 51, Fig. 8).
Regarding claim 14, Yamaguchi further discloses that each hole (each 54, Fig. 8) of the first series of holes (grooves 54 on the left edge of 51, Fig. 8) and each hole (each 54, Fig. 8) of the second series of holes (grooves 54 on the right edge of 51, Fig. 8) has a perimeter bounded by an arc and a chord of a circle, because the grooves 54 by Yamaguchi has semicircular shape, and therefore, it has a perimeter bounded by an arc and a chord of a circle.
Regarding claim 16, Yamaguchi further discloses for a memory device comprising that a circuit substrate (interposer substrate 51, Fig. 8) comprising a first substrate surface (top surface of 51, Fig. 8), a second substrate surface (bottom surface of 51, Fig. 8) arranged opposite to the first substrate surface (top surface of 51, Fig. 8), a first substrate edge (left edge of 51, Fig. 8) that extends from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8), and a second substrate edge (right edge of 51, Fig. 8) that extends from the first substrate surface (top surface of 51, Fig. 8) to the second substrate surface (bottom surface of 51, Fig. 8) and is arranged opposite to the first substrate edge (opposite to the left edge of 51, Fig. 8),
wherein a first series of holes (grooves 54 on the left edge of 51, Fig. 8) is arranged along the first substrate edge of the circuit substrate (left edge of 51, Fig. 8) to form a first perforated edge (left edge of 51, Fig. 8),
wherein each hole (each 54, Fig. 8) of the first series of holes (54 on the left edge of 51, Fig. 8) extends at least partially from the first substrate surface (top surface of 51, Fig. 8) toward the second substrate surface (bottom surface of 51, Fig. 8),
wherein a second series of holes (grooves 54 on the right edge of 51, Fig. 8) is arranged along the second substrate edge of the circuit substrate (right edge of 51, Fig. 8) to form a second perforated edge (right edge of 51, Fig. 8),
wherein each hole (each 54, Fig. 8) of the second series of holes (54 on the right edge of 51, Fig. 8) extends at least partially from the first substrate surface (top surface of 51, Fig. 8) toward the second substrate surface (bottom surface of 51, Fig. 8);
at least one memory die (semiconductor substrate 41 including an active region 42, Fig. 8) arranged on the first substrate surface (top surface of 51, Fig. 8).
Yamaguchi does not explicitly disclose that a package molding disposed on the first substrate surface, wherein the package molding is in direct contact with the first substrate edge in each hole of the first series of holes and encapsulates the at least one memory die and the first substrate surface, and wherein the package molding fills the first series of holes and the second series of holes.
However, Lee discloses an die paddle 534 including a plurality of marginal recesses 575 formed along edges of the die paddle 534 and extended at least partially from the upper surface toward the lower surface of the die paddle (Fig. 5A-5B), and because Applicants do not specifically claim what material’s composition and/or structural configuration the circuit substrate has, the die paddle 534 and the marginal recesses by Lee correspond to the circuit substrate and series of holes in the claimed invention, respectively. Lee further discloses that the plastic encapsulation (370, Fig. 3A) is disposed over an upper surface of the die paddle (Fig. 3A), therefore, the encapsulation material by Lee corresponds to the package molding in the claimed invention; in view of Fig. 3A in Lee, the encapsulation material is disposed in direct contact with the plurality of marginal recesses 575, encapsulates the semiconductor die (340) and top surface of the die paddle 534, and fills each marginal recess of the plurality of marginal recesses 575 (Fig. 5A). Therefore, Lee teaches a semiconductor assembly through the filled marginal recesses formed along the edge of die paddle, thereby providing a mechanical interlocking structure between the package molding and the circuit substrate, and one of ordinary skill in the semiconductor packaging art would have recognized that such a mechanical interlocking structure improve mechanical stability and/or adhesion between the packaging molding and the substrate.
Since both Yamaguchi and Lee teach a semiconductor chip assembly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the semiconductor packaging having marginal recesses-interlocking mechanism of Lee into the semiconductor device assembly by Yamaguchi, in order to improve mechanical stability and structural integrity of the overall assembly.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
Prosecution Insights