DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 12/06/2023.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/06/2023, 02/11/2025, 04/15/2025 and 04/24/2026 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8, 11-12 and 14 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2021/0193829 A1 (Reznicek).
Regarding claim 1, Reznicek discloses, a semiconductor device comprising:
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a nanosheet stack (as annotated on Fig. 14B; [0110]) disposed on a substrate (100);
a source/drain epitaxial layer (1010; source/drain epitaxy; Fig. 14B; [0110]) disposed on the substrate (100) adjacent to the nanosheet stack; and
a source/drain contact (1410; source/drain contact; Fig. 14B and 14C; [0110]) formed in contact with the source/drain epitaxial layer (1010),
the source/drain contact (1410) including a wrap-around portion that wraps around sidewall surfaces (as evident in Fig. 14C) of the source/drain epitaxial layer (1010) (Fug. 14C; [0110]), and
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an extending portion (extending upward, as annotated on Fig. 14C; [0110]) that extends from the wrap-around portion (as annotated on Fig. 14C; [0110]),
wherein the wrap-around portion has a non-uniform thickness (as evident in Fig. 14C).
Regarding claim 2, Reznicek discloses, the semiconductor device of claim 1, wherein the wrap-around portion of the source/drain contact (1410) includes a first section and a second section (as annotated on Fig. 14C), the second section of the wrap-around portion being nearer to the extending portion than the first section of the wrap-around portion (as evident in Fig. 14C), and wherein the first section of the wrap-around portion has a first thickness, and the second section of the wrap-around portion has a second thickness that is greater than the first thickness (Fig. 14C; [0110]).
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Regarding claim 5, Reznicek discloses, the semiconductor device of claim 2, further comprising a source/drain placeholder layer (810; Ge layer; Fig. 10B; [0084]) in contact with a side of the source/drain epitaxial layer (1010) that is opposite to a side on which the extending portion of the source/drain contact is located (Fig. 14C).
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Regarding claim 8, Reznicek discloses, the semiconductor device of claim 2, further comprising:
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a second source/drain epitaxial layer disposed on the substrate adjacent to the nanosheet stack;
a second source/drain contact formed in contact with the second source/drain epitaxial layer, the second source/drain contact including a second wrap-around portion that covers sidewall surfaces of the second source/drain epitaxial layer, and
a second extending portion that extends from the second wrap-around portion in a second extending direction that is opposite to a first extending direction of the extending portion, wherein the second wrap-around portion has a non-uniform thickness (Reznicek teaches multiple source/drain epitaxial layers and source/drain contacts. One of them can be second source/drain).
Regarding claim 11, Reznicek discloses, the semiconductor device of claim 8, wherein the second wrap-around portion of the second source/drain contact also covers a surface of the second source/drain epitaxial layer that is opposite to a side that the second extending portion is located (Fig. 14C teaches it).
Regarding claim 12, Reznicek discloses, the semiconductor device of claim 1, wherein the nanosheet stack (as annotated on Fig. 14B) includes a gate electrode (1210; gate structure; Fig. 14B; [0110]).
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Regarding claim 14, Reznicek discloses, the semiconductor device of claim 2, wherein a transition between the first section of the wrap-around portion and the second section of the wrap-around portion is at a middle level of the source/drain epitaxial layer (Fig. 14C; [0110]; the transition point can be taken as the middle level of the source/drain epitaxial layer 1010. Therefore, it can be considered that the limitation is taught by Reznicek).
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Claims 15-16 and 19 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2021/0193829 A1 (Reznicek).
Regarding claim 15, Reznicek discloses, an electronic device comprising: a semiconductor device (semiconductor structure; Fig. 14; [0110]) including a nanosheet stack (as annotated on Fig. 14B; [0110]) disposed on a substrate (100);
a source/drain epitaxial layer (1010; source/drain epitaxy; Fig. 14B; [0110]) disposed on the substrate (100) adjacent to the nanosheet stack; and
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a source/drain contact (1410; source/drain contact; Fig. 14B and 14C; [0110]) formed in contact with the source/drain epitaxial layer (1010),
the source/drain contact (1410) including a wrap-around portion that wraps around sidewall surfaces (as evident in Fig. 14C) of the source/drain epitaxial layer (1010) (Fug. 14C; [0110]), and
an extending portion (extending upward, as annotated on Fig. 14C; [0110]) that extends from the wrap-around portion (as annotated on Fig. 14C; [0110]),
wherein the wrap-around portion has a non-uniform thickness (as evident in Fig. 14C).
Regarding claim 16, Reznicek discloses, the electronic device of claim 15, wherein the wrap-around portion of the source/drain contact (1410) includes a first section and a second section (as annotated on Fig. 14C), the second section of the wrap-around portion being nearer to the extending portion than the first section of the wrap-around portion, and wherein the first section of the wrap-around portion has a first thickness, and the second section of the wrap-around portion has a second thickness that is greater than the first thickness (Fig. 14C; [0110]).
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Regarding claim 19, Reznicek discloses, the electronic device of claim 16, further comprising:
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a second source/drain epitaxial layer disposed on the substrate adjacent to the nanosheet stack;
a second source/drain contact formed in contact with the second source/drain epitaxial layer, the second source/drain contact including a second wrap-around portion that covers sidewall surfaces of the second source/drain epitaxial layer, and
a second extending portion that extends from the second wrap-around portion in a second extending direction that is opposite to a first extending direction of the extending portion, wherein the second wrap-around portion has a non-uniform thickness (Reznicek teaches multiple source/drain epitaxial layers and source/drain contacts. One of them can be second source/drain).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193829 A1 (Reznicek) and further in view of US 2025/0006557 A1 (Huang).
Regarding claim 3, Reznicek fails to teach explicitly, the semiconductor device of claim 1, wherein the extending portion of the source/drain contact is connected to a back end of line (BEOL) layer.
However, in analogous art, Huang discloses, the semiconductor device of claim 1, wherein the extending portion of the source/drain contact is connected to a back end of line (BEOL) layer ([0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Reznicek and Huang before him/her, to modify the teachings of a semiconductor device using source/drain contacts as taught by Reznicek and to include the teachings of extending portion of the source/drain contact is connected to a back end of line (BEOL) layer as taught by Huang since the source/drain contacts need to be connected to interconnects through BEOL for circuit operation and absent this important teaching in Reznicek, a person with ordinary skill in the art would be motivated to reach out to Huang while forming a semiconductor device of Reznicek.
Regarding claim 4, Reznicek fails to teach explicitly, the semiconductor device of claim 1, wherein the extending portion of the source/drain contact is connected to a backside power distribution network (BSPDN).
However, in analogous art, Huang discloses, the semiconductor device of claim 1, wherein the extending portion of the source/drain contact is connected to a backside power distribution network (BSPDN) (250; backside power rail; Fig. 15; [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Reznicek and Huang before him/her, to modify the teachings of a semiconductor device using source/drain contacts as taught by Reznicek and to include the teachings of extending portion of the source/drain contact is connected to a backside power rail as taught by Huang since the source/drain contacts need to be connected to interconnects through BEOL for circuit operation and absent this important teaching in Reznicek, a person with ordinary skill in the art would be motivated to reach out to Huang while forming a semiconductor device of Reznicek.
Regarding claim 10, Reznicek fails to teach explicitly, the semiconductor device of claim 8, wherein the extending portion of the source/drain contact is connected to a BEOL layer, and wherein the second extending portion of the second source/drain contact is connected to a BSPDN.
However, in analogous art, Huang discloses, the semiconductor device of claim 1, the semiconductor device of claim 8, wherein the extending portion of the source/drain contact is connected to a BEOL layer ([0042]), and wherein the second extending portion (as annotated on Fig. 15) of the second source/drain contact is connected to a BSPDN (250; backside power rail; Fig. 15; [0042]).
Note: The examiner notes that with the teaching of Huang in para. [0042], it is well within the purview of a person with ordinary skill in the art to connect one source/drain contact connected to a BEOL layer and the other source/drain contact connected to a backside power distribution network BSPDN.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Reznicek and Huang before him/her, to modify the teachings of a semiconductor device using source/drain contacts as taught by Reznicek and to include the teachings of extending portion of the source/drain contact is connected to a BEOL or a backside power rail as taught by Huang since the source/drain contacts need to be connected to interconnects through BEOL or a backside power rail for circuit operation and absent this important teaching in Reznicek, a person with ordinary skill in the art would be motivated to reach out to Huang while forming a semiconductor device of Reznicek.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193829 A1 (Reznicek) as applied to claim 12 and further in view of US 2021/0375691 A1 (Chen).
Regarding claim 13, Reznicek fails to teach explicitly, the semiconductor device of claim 12, further comprising: a SiOC based gate cap formed on the gate electrode; and a SiOC based gate spacer formed on sidewalls of the gate electrode and the gate cap.
However, in analogous art, Chen discloses, the semiconductor device of claim 12, further comprising: a SiOC based gate cap (124; [0029]) formed on the gate electrode (122); and a SiOC based gate spacer (108; [0028]) formed on sidewalls of the gate electrode (122) and the gate cap (124) (Fig. 2D; [0028] – [0029]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Reznicek and Chen before him/her, to modify the teachings of a semiconductor device using gate structures as taught by Reznicek and to include the teachings of SiOC based gate cap and SiOC based gate spacer as taught by Chen since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Reznicek, a person with ordinary skill in the art would be motivated to reach out to Chen while forming a semiconductor device of Reznicek.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193829 A1 (Reznicek) and further in view of US 2025/0006557 A1 (Huang).
Regarding claim 17, Reznicek fails to teach explicitly, the electronic device of claim 15, wherein the extending portion of the source/drain contact is connected to a back end of line (BEOL) layer.
However, in analogous art, Huang discloses, the electronic device of claim 15, wherein the extending portion of the source/drain contact is connected to a back end of line (BEOL) layer ([0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Reznicek and Huang before him/her, to modify the teachings of a semiconductor device using source/drain contacts as taught by Reznicek and to include the teachings of extending portion of the source/drain contact is connected to a back end of line (BEOL) layer as taught by Huang since the source/drain contacts need to be connected to interconnects through BEOL for circuit operation and absent this important teaching in Reznicek, a person with ordinary skill in the art would be motivated to reach out to Huang while forming a semiconductor device of Reznicek.
Regarding claim 18, Reznicek fails to teach explicitly, the electronic device of claim 15, wherein the extending portion of the source/drain contact is connected to a backside power distribution network (BSPDN).
However, in analogous art, Huang discloses, the electronic device of claim 15, wherein the extending portion of the source/drain contact is connected to a backside power distribution network (BSPDN) (250; backside power rail; Fig. 15; [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Reznicek and Huang before him/her, to modify the teachings of a semiconductor device using source/drain contacts as taught by Reznicek and to include the teachings of extending portion of the source/drain contact is connected to a backside power rail as taught by Huang since the source/drain contacts need to be connected to interconnects through BEOL for circuit operation and absent this important teaching in Reznicek, a person with ordinary skill in the art would be motivated to reach out to Huang while forming a semiconductor device of Reznicek.
Allowable Subject Matter
Claims 6-7, 9 and 20 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 6, the closest prior art, US 2021/0193829 A1 (Reznicek), in combination with US 2025/0006557 A1 (Huang) and US 2021/0375691 A1 (Chen), in combination with the other claimed features, fails to disclose, “the semiconductor device of claim 5, further comprising: a first STI liner layer in contact with sidewalls of the source/drain placeholder layer; and a second STI liner layer in contact with the first STI liner layer, the sidewalls of the source/drain placeholder layer, and the wrap-around portion of the source/drain contact”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claim 7 is also objected to due to its dependence on an objected base claim.
Regarding claim 9, the closest prior art, US 2021/0193829 A1 (Reznicek), in combination with US 2025/0006557 A1 (Huang) and US 2021/0375691 A1 (Chen), in combination with the other claimed features, fails to disclose, “the semiconductor device of claim 8, wherein the second wrap-around portion of the second source/drain contact includes a first section and a second section, the second section of the second wrap-around portion being nearer to the second extending portion than the first section of the second wrap-around portion, and wherein the first section of the second wrap-around portion has the third thickness, and the second section of the second wrap-around portion has the first thickness, where the second thickness is greater than the first thickness which is greater than the third thickness”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 20, the closest prior art, US 2021/0193829 A1 (Reznicek), in combination with US 2025/0006557 A1 (Huang) and US 2021/0375691 A1 (Chen), in combination with the other claimed features, fails to disclose, “the electronic device of claim 19, wherein the second wrap-around portion of the second source/drain contact includes a first section and a second section, the second section of the second wrap-around portion being nearer to the second extending portion than the first section of the second wrap-around portion, and wherein the first section of the second wrap-around portion has the third thickness, and the second section of the second wrap-around portion has the first thickness, where the second thickness is greater than the first thickness which is greater than the third thickness”, in combination with the additionally claimed features, as are claimed by the Applicant.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2025/0132246 A1 (Liu) - A semiconductor structure and a method of forming the same are provided. The method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.
US 2022/0310455 A1 (Huang) - A semiconductor structure and a method of forming the same are provided. The method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.
US 2021/0193842 A1 (Wang) - A semiconductor device is provided that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
04/28/2026
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