DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 3/31/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 4 recites “respective semiconductor chips”. It is not clear, from this limitation, whether these are intended to be the same as the “plurality of semiconductor devices” of lines 2-3 of claim 1 or are intended to be different devices. This issue renders the claim indefinite.
Claim 3, lines 4-5 recite “apertures provided at said tie bars”. It is not clear, from this limitation, whether the “apertures” are the same as those from claim 1 or are intended to be new apertures. It is also not clear how the apertures can be “at said tie bars” since the apertures are in the connecting bars which are different parts than the tie bars. This issue renders the claim indefinite.
Claim 5, lines 3-4 recite “respective semiconductor chips” and “apertures … at said die pads”. It is not clear, from this limitation, whether the “semiconductor chips” are the same as those from claim 1 or are intended to be new chips. It is also not clear how the apertures can be “at said die pads” since the apertures are in the connecting bars which are different parts than the die pads. This issue renders the claim indefinite.
Claim 5, lines 2 and 5 recites “respective semiconductor chips”. It is not clear, from this limitation, whether the “semiconductor chips” are the same as those from claim 1 or are intended to be new chips. This issue renders the claim indefinite.
Claim 10, line 5recites “mutually facing sides”. It is not clear, from this limitation, whether the “mutually facing sides” are the same as those from claim 1 or are intended to be new sides. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 and 20-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FUKUSHIMA (US 20100244210).
Regarding claim 1, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses amethod, comprising:
providing a common electrically conductive substrate (fig 1, 10, para 27) for a plurality of semiconductor devices (fig 1-3, 44, para 46),
wherein the common electrically conductive substrate comprises a plurality of first substrate portions (fig 1, 12, para 26) configured to host respective semiconductor chips (fig 1-3, 44, para 46),
wherein adjacent first substrate portions in the common electrically conductive substrate have mutually facing sides (the sides of 12 that face each other, see fig 1B and figure I below) with elongate sacrificial connecting bars (portions 14 and 16 of frame 10 between each block 12, see fig 1B and figure I below and para 36) extending between the mutually facing sides;
providing the elongate sacrificial connecting bars with an apertured structure comprising apertures (the holes and grooves 22, 24 and 34, see fig 1B, para 34 and 40) distributed along a length of the elongate sacrificial connecting bars at locations between the mutually facing sides of the adjacent first substrate portions (some of the apertures 22, 24 and 34 are present in the portions of 10 between 12, see fig 1B and figure I below); and
cutting the common electrically conductive substrate along the length of the elongate sacrificial connecting bars to provide singulated individual substrate portions (14 and 16 are cut along lines 18 and 20 to separate the portions 12, see fig 1B, para 31 and figure I below).
Regarding claim 2, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, wherein the apertures comprise slits extending transverse the elongate sacrificial connecting bars (the slits 24 extend transverse to 16 and the slits 22 extends transverse to 14, see fig 1B, para 34 and figure I below).
Regarding claim 3, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, further comprising
providing tie bars distributed along the length of the elongate sacrificial connecting bars (the portions of 10 between 34 that connect 12 and 14 or 16, see fig 1B and figure I below) and
coupling the elongate connecting bars to facing sides of the adjacent first substrate portions in the common electrically conductive substrate (portions of 10 couple 16 to 12, see fig 1B and figure I below),
wherein the apertured structure of the elongate sacrificial connecting bars comprises apertures provided at said tie bars (apertures 24 and the portions of 10 are located along the same lines 18, see fig 1B and figure I below).
Regarding claim 4, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 3, wherein the apertures provided at tie bars comprise terminal ends of the apertures extending into the tie bars (the ends of 24 are aligned with the portions of the substrate 10 along lines 18, see fig 1B and figure I below).
Regarding claim 5, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, wherein
the plurality of first substrate portions in the common electrically conductive substrate comprise die pads (each block 12 comprises units 26 with islands 28, see fig 1-3, para 41) configured to host respective semiconductor chips (the islands 28 can have chips 44, see fig 1-3, para 46),
wherein the method comprises providing apertures distributed along the length of the elongate sacrificial connecting bars at said die pads (the apertures 24 are aligned with the units 26 along the horizontal and vertical directions, see fig 1B).
Regarding claim 6, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, further comprising
molding a molding compound onto the common electrically conductive substrate (the sealing resin 36, see fig 4-5, para 57),
wherein the molding compound penetrates into the apertured structure of the elongate sacrificial connecting bars (see para 57).
Regarding claim 7, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 6, further comprising
cutting through the common electrically conductive substrate along the length of the elongate sacrificial connecting bars with the molding compound penetrated into the apertured structure of the elongate sacrificial connecting bars (see fig 6-7, para 63).
Regarding claim 8, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, further comprising:
providing respective semiconductor chips (fig 1-3, 44, para 47) at the plurality of substrate portions in the common electrically conductive substrate; and
cutting along the length of the elongate sacrificial connecting bars (cuts 20 and 18 are made along the lengths of 14 and 16, see fig 1, para 33),
wherein the common electrically conductive substrate has respective semiconductor chips provided at the plurality of substrate portions (44 are provided in each block 12, see fig 1, para 47).
Regarding claim 9, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, wherein the apertures comprise openings which pass completely through a thickness of the elongate sacrificial connecting bars (24 penetrate entirely through the metal of 10, see fig 1, para 36).
Regarding claim 10, as best as the examiner is able to ascertain the claimed invention, FUKUSHIMA discloses the method of claim 1, wherein
the common electrically conductive substrate further comprises a plurality of second substrate portions configured to provide electrical leads (fig 1-3, 30, para 41),
wherein adjacent second substrate portions in the common electrically conductive substrate have mutually facing sides with elongate sacrificial connecting bars extending between the mutually facing sides (the bars 14 and 16 are provided between facing sides of 12 and 30 are also present in 12, see fig 1-3, para 41), and
wherein the apertures distributed along the length of the elongate sacrificial connecting bars are not present at the second substrate portions configured to provide electrical leads (the apertures 22, 24 and 34 are not present in 30, see fig 2).
Regarding claim 20, FUKUSHIMA discloses a method, comprising:
providing a common leadframe (fig 1, 10, para 27) including a first die pad (the left block 12 in fig 1B contains units 26 with die pads 28, see fig 1-3, para 26 and 41 and figure I below) and second die pad (the right block 12 contains units 26 with die pads 28, see fig 1-3, para 26 and 41) configured to host respective semiconductor chips,
said first and second die pads have mutually facing sides (the sides of 12 that face each other, see fig 1B and figure I below),
said common leadframe further including a connecting bar (portions 14 and 16 of frame 10 between each block 12, see fig 1B and figure I below and para 36) positioned between the first die pad and the second die pad and extending parallel to the mutually facing sides,
said common leadframe further including a first tie bar (a portion of 10 between 34 that connect 12 and 14 or 16, see fig 1B and figure I below) having a first end connected to the first die pad and a second end connected to the connecting bar and a second tie bar (another portion of 10 between 34 that connect 12 and 14 or 16, see fig 1B and figure I below) having a first end connected to the second die pad and a second end connected to the connecting bar;
providing a first aperture extending into the connecting bar at a position where the second end of the first tie bar connects to the connecting bar (the portions of 10 that connect 12 and 14 are aligned with apertures 24, see fig 1B, para 34 and figure I below);
providing a second aperture extending into the connecting bar at a position where the second end of the second tie bar connects to the connecting bar (the portions of 10 that connect 12 and 14 are aligned with apertures 24, see fig 1B, para 34 and figure I below); and
cutting the common leadframe along the length of the connecting bar to provide singulated leadframe portions (14 and 16 are cut along lines 18 and 20 to separate the portions 12, see fig 1B, para 31 and figure I below).
Regarding claim 21, FUKUSHIMA discloses the method of claim 20, wherein providing the first aperture comprises having a slit formed by the first aperture extend into the first tie bar and wherein providing the second aperture comprises having a slit formed by the second aperture extend into the second tie bar (the apertures 24 are slits that extend into the portions of 10, see fig 1B and figure I below).
Regarding claim 22, FUKUSHIMA discloses the method of claim 20, wherein each of the first and second apertures comprise a slits extending transverse to the mutually facing sides of the first and second die pads (the sides of the die pads have an extension in the y-direction fig 1B, and the slits extend in the x direction in fig 1B, see fig 1-3).
Regarding claim 23, FUKUSHIMA discloses the method of claim 20, further comprising molding a molding compound onto the common leadframe (the sealing resin 36, see fig 4-5, para 57), wherein the molding compound penetrates into the first and second apertures (see para 57).
Regarding claim 24, FUKUSHIMA discloses the method of claim 23, wherein cutting the common leadframe comprises cutting through the molding compound within the first and second apertures (see fig 6-7, para 63).
Regarding claim 25, FUKUSHIMA discloses the method of claim 20, wherein each of the first and second apertures comprise openings which pass completely through a thickness of the connecting bar (24 passes entirely through the metal of 10, see fig 1B, para 36).
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Figure I: FUKUSHIMA figure 1B with added annotations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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