DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 6 and 16, the limitation “wherein each of the n-type transistor and the p-type transistor comprises two finger sub-devices which share a second dielectric barrier extending between the respective finger sub-devices” renders the claim indefinite, as how the n-type transistor and the p-type transistor can each comprise two sub-devices sharing a single second dielectric barrier is unclear, and the relationship of these to the dielectric barrier already specified in claim 1 and 11 is further unclear. This claim appears to correspond to the embodiment of Fig. 1C. In light of that, the claims will be interpreted as “wherein one of the n-type transistor and the p-type transistor comprises two finger sub-devices which share the dielectric barrier extending between the two finger sub-devices, and the other of the n-type transistor and the p-type transistor comprises two finger sub-devices which share a second dielectric barrier extending between the two finger sub-devices”.
Regarding claim 11, the limitation “forming a plurality of stacked semiconductors … wherein each finger sub-device … comprises a plurality of stacked semiconductors” renders the claim indefinite, as it is unclear if/how the second set of stacked semiconductors relates to the first set of stacked semiconductors. For purposes of examination, the limitation will be interpreted as “wherein each finger sub-device …comprises the plurality of stacked semiconductors”
Further, the limitation “etching a top and at least one side of each finger sub-device of the plurality of finger sub-devices, leaving a dielectric barrier” renders the claim indefinite. It is unclear what is being etched, and no element is previously recited which could be etched to “leave” a dielectric barrier in place. The limitation will be interpreted as best understood in light of the specification as “forming a dielectric layer over the plurality of finger sub-devices, etching the dielectric layer from a top and at least one side of each of the plurality of finger sub-devices, leaving a dielectric barrier extending down only one side of a subset of the stacked semiconductors”. Claims 12-19 depend from and further limit claim 11 and are therefore correspondingly indefinite.
Correspondingly, for claim 15 the limitations “wherein the etching of a finger sub-device of the n-type transistor” and “wherein the etching of a finger sub-device of the p-type transistor” will be interpreted respectively as “wherein the etching of the dielectric layer over a finger sub-device of the n-type transistor” and “wherein the etching of the dielectric layer over a finger sub-device of the p-type transistor”.
Regarding claim 13, the limitation “the finger sub-devices which are not formed as fork stack devices” renders the claim indefinite, as no finger sub-devices which are not formed as fork stack devices have been specified previously. For purposes of examination, the claim will be interpreted as “wherein the etching and depositing steps are configured to form a subset of the plurality of finger sub-devices as gate-all-around devices…”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 11, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng (U.S. PGPub 2022/0130955).
Regarding claims 1 and 6, Cheng teaches a semiconductor architecture, comprising a substate, an n-type transistor and a p-type transistor, wherein each of the n-type transistor and the p-type transistor are formed on the substrate, wherein each of the n-type transistor and the p-type transistor comprises a plurality of finger sub-devices, wherein each finger sub-device of the plurality of finger sub-devices comprises a plurality of stacked semiconductors, wherein one or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors, wherein one of the n-type transistor and the p-type transistor comprises two finger sub-devices which share the dielectric barrier extending between the two finger sub-devices, and the other of the n-type transistor and the p-type transistor comprises two finger sub-devices which share a second dielectric barrier extending between the two finger sub-devices (Fig. 23, substrate 202, stacked semiconductors 2080, n-type transistor 302, p-type transistor 308, finger sub-devices 270-1, 270-2, 270-3, 270-4, dielectric barriers 230, [0018]-[0038]).
Regarding claims 11 and 16, Cheng teaches a method of manufacturing a semiconductor architecture, comprising providing a substrate, forming a plurality of stacked semiconductors on the substrate to form an n-type transistor and a p-type transistor on the substrate, wherein each of the n-type transistor and the p-type transistor comprises a plurality of finger sub-devices, and each finger sub-device of the plurality of finger sub-devices comprises a plurality of stacked semiconductors (Fig. 3, 208, [0015]-[0016], 202P/202N), depositing a gate dielectric layer (Fig. 20, 268, [0035]), forming a dielectric layer over the plurality of finger sub-devices, etching the dielectric layer from a top and at least one side of each of the plurality of finger sub-devices, leaving a dielectric barrier extending down only one side of a subset of the stacked semiconductors (Figs. 8-9, 224/226, 230, [0022]-[0023]), and depositing one or more metal gate layers, wherein one or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising the dielectric barrier extending down only one side of the stacked semiconductors, wherein one of the n-type transistor and the p-type transistor comprises two finger sub-devices which share the dielectric barrier extending between the two finger sub-devices, and the other of the n-type transistor and the p-type transistor comprises two finger sub-devices which share a second dielectric barrier extending between the two finger sub-devices (Fig. 23, n-type transistor 302, p-type transistor 308, sub-devices 270-1, 270-2, 270-3, 270-4, [0036]-[0038]).
Claims 1-4, 7-14, and 17-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu (U.S. PGPub 2022/0302275).
Regarding claim 1, Yu teaches a semiconductor architecture, comprising a substate, an n-type transistor and a p-type transistor, wherein each of the n-type transistor and the p-type transistor are formed on the substrate, wherein each of the n-type transistor and the p-type transistor comprises a plurality of finger sub-devices, wherein each finger sub-device of the plurality of finger sub-devices comprises a plurality of stacked semiconductors, wherein one or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors (Fig. 31, n-type transistor 112b, p-type transistor 112a and 112c, [0055], [0087], stacked semiconductors 106, [0028], dielectric barrier 141, [0045])
Regarding claim 2, Yu teaches wherein three sides of each fork stack device are surrounded by a gate dielectric layer and an n-type metal gate layer or a p-type metal gate layer (Fig. 31, 180, 182/184, [0062], [0071], [0076])
Regarding claim 3, Yu teaches wherein each of the finger sub-devices of the plurality of finger sub-devices which are not formed as fork stack devices are formed as gate-all-around devices, and wherein all four sides of each fork stack device are surrounded by the gate dielectric layer and the n-type metal gate layer or the p-type metal gate layer (Fig. 31, 112a).
Regarding claim 4, Yu teaches wherein a finger sub-device of the n-type transistor and a finger sub-device of the p-type transistor share the dielectric barrier which extends between the n-type transistor and the p-type transistor (Fig. 31, 112b/112c).
Regarding claim 7, Yu teaches wherein each of the n-type transistor and the p-type transistor comprises a total of two finger sub-devices (Fig. 35, forksheet transistors 211, 212, same as in Fig. 31).
Regarding claim 8, Yu teaches wherein each of the finger sub-devices of the plurality finger sub-devices includes a total of three stacked semiconductors (Fig. 31).
Regarding claims 9-10, the Office reminds Applicant that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. See MPEP 2113(I). It is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. Note that applicant has the burden of proof in such cases. See MPEP 2113(II). Thus, no patentable weight will be given to those process steps which do not add structural limitations to the final product. Yu teaches the structure formed by the method (Fig. 31, stacked semiconductors 106, [0028], gate dielectric 180, [0062], dielectric barrier 141, [0045], n-type and p-type metal gate layers 182/184, [0071], [0076]).
Regarding claim 11, Yu teaches a method of manufacturing a semiconductor architecture, comprising providing a substrate, forming a plurality of stacked semiconductors on the substrate to form an n-type transistor and a p-type transistor on the substrate, wherein each of the n-type transistor and the p-type transistor comprises a plurality of finger sub-devices, and each finger sub-device of the plurality of finger sub-devices comprises the plurality of stacked semiconductors (substrate 101, [0018]; stacked semiconductors, 106, [0028]; Fig. 16A, n-type transistor 112b, p-type transistor 112a and 112c, [0055]), depositing a gate dielectric (180, [0062]), forming a dielectric layer over the plurality of finger sub-devices, etching the dielectric layer from a top and at least one side of each of the plurality of finger sub-devices, leaving a dielectric barrier extending down only one side of a subset of the stacked semiconductors (Figs. 6-11, [0044]-[0046], 141), and depositing one or more metal gate layers, wherein one or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising the dielectric barrier extending down only one side of the stacked semiconductors (Fig. 31, n-type and p-type metal gate layers 182/184, [0071], [0076]).
Regarding claim 12, Yu teaches wherein the etching and depositing steps are configured to surround three sides of each fork stack device with a gate dielectric layer and an n-type metal gate layer or a p-type metal gate layer (Fig. 31, 180, 182/184, [0062], [0071], [0076]).
Regarding claim 13, Yu teaches wherein the etching and depositing steps are configured to form a subset of the plurality of finger sub-devices as gate-all-around devices, wherein all four sides are surrounded by the gate dielectric layer and the n-type metal gate layer or the p-type metal gate layer (Fig. 31, 112a).
Regarding claim 14, Yu teaches wherein the etching of a finger sub-device of the n-type transistor and a finger sub-device of the p-type transistor forms the dielectric barrier which extends between the n-type transistor and the p-type transistor (Figs. 6-11, [0044]-[0046], 141).
Regarding claim 17, Yu teaches wherein each of the n-type transistor and the p-type transistor comprises a total of two finger sub-devices (Fig. 35, forksheet transistors 211, 212, same as in Fig. 31).
Regarding claim 18, Yu teaches wherein each of the finger sub-devices of the plurality of finger sub-devices includes a total of three stacked semiconductors (Fig. 31).
Regarding claim 19, Yu teaches wherein depositing the one or more metal gate layers comprises depositing an n-type metal gate layer, etching the n-type metal gate layer, and depositing a p-type metal gate layer (Figs. 26-29, n-type and p-type metal gate layers 182/184, [0070]-[0076]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (U.S. PGPub 2022/0302275) in view of Hirose (U.S. PGPub 2022/0375945).
Regarding claim 5, Yu does not explicitly teach wherein a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor.
Hirose teaches two n-type and two p-type finger sub-devices comprising forksheet FETs, wherein one of the finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors, a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor (Figs. 1A-1B, P11/P12/N11/N12, [0037], [0049]-[0052]), see annotated Fig. 1B with the locations of the dielectric barriers shown, compare with Fig. 1B of the instant application.
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hirose with Yu such that a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor for the purpose of forming a standard cell comprising forksheet transistors formed according to the method of Yu (Hirose, [0037], [0035]).
Regarding claim 15, Yu does not explicitly teach wherein the etching of the dielectric layer over a finger sub-device of the n-type transistor which is distal from the p-type transistor forms a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and wherein the etching of the dielectric layer over a finger sub-device of the p-type transistor which is distal from the n-type transistor forms a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor.
Hirose teaches two n-type and two p-type finger sub-devices comprising forksheet FETs, wherein one of the finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors, a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor (Figs. 1A-1B, P11/P12/N11/N12, [0037], [0049]-[0052]), see annotated Fig. 1B with the locations of the dielectric barriers shown, compare with Fig. 1B of the instant application.
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hirose with Yu the etching of the dielectric layer over a finger sub-device of the n-type transistor which is distal from the p-type transistor forms a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and wherein the etching of the dielectric layer over a finger sub-device of the p-type transistor which is distal from the n-type transistor forms a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor for the purpose of forming a standard cell comprising forksheet transistors formed according to the method of Yu (Hirose, [0037], [0035]).
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812