DETAILED ACTION
Response to Amendment
The citation of reference Hirose, U.S. PGPub 2022/0375945, in the previous Office action, was a typographical error and the correct reference is Iwahori, U.S. PGPub 2022/0216319. The rejection has been updated to correct this error.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 6, 13, and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claims 1 and 11 require three dielectric barriers extending down a side of stacked semiconductors to form respective finger sub-devices, corresponding to the embodiment of Fig. 1B. Dependent claims 3 and 13 require a subset of finger sub-device which are formed as gate-all-around devices, corresponding to the embodiment of Fig. 1A. Dependent claims 6 and 16 require two dielectric barriers, each having two finger sub-devices sharing the respective dielectric barrier, corresponding to the embodiment of Fig. 1C.
Applicant has not disclosed an embodiment or configuration that comprises the limitations of claims 1 and 3, 1 and 6, 11 and 13, or 11 and 16 together. The subject matter in these claims together is not supported by the original disclosure so as to show to the person of ordinary skill that the inventors had possession of the invention at the time it was filed.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4, 7-12, 14, and 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (U.S. PGPub 2022/0302275) in view of Iwahori (U.S. PGPub 2022/0216319).
Regarding claim 1, Yu teaches a semiconductor architecture, comprising a substate, an n-type transistor and a p-type transistor, wherein each of the n-type transistor and the p-type transistor are formed on the substrate, wherein each of the n-type transistor and the p-type transistor comprises a plurality of finger sub-devices, wherein each finger sub-device of the plurality of finger sub-devices comprises a plurality of stacked semiconductors, wherein one or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors (Fig. 31, n-type transistor 112b, p-type transistor 112a and 112c, [0055], [0087], stacked semiconductors 106, [0028], dielectric barrier 141, [0045]).
Yu does not explicitly teach wherein a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor.
Iwahori teaches two n-type and two p-type finger sub-devices comprising forksheet FETs, wherein one of the finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors, a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor (Figs. 1A-1B, P11/P12/N11/N12, [0037], [0049]-[0052]; dielectric barriers not depicted but forksheet FETs are defined by the presence of a dielectric barrier contacting the side of stacked nanosheets), see annotated Fig. 1B with the locations of the dielectric barriers shown, compare with Fig. 1B of the instant application.
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hirose with Yu such that a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor for the purpose of forming a standard cell comprising forksheet transistors formed according to the method of Yu (Hirose, [0037], [0035]).
Regarding claim 2, the combination of Yu and Iwahori teaches wherein three sides of each fork stack device are surrounded by a gate dielectric layer and an n-type metal gate layer or a p-type metal gate layer (Yu, Fig. 31, 180, 182/184, [0062], [0071], [0076]; Iwahori, [0049]-[0050]).
Regarding claim 4, the combination of Yu and Iwahori teaches wherein a finger sub-device of the n-type transistor and a finger sub-device of the p-type transistor share the dielectric barrier which extends between the n-type transistor and the p-type transistor (Yu, Fig. 31, 112b/112c; Iwahori, Fig. 1B).
Regarding claim 7, the combination of Yu and Iwahori teaches wherein each of the n-type transistor and the p-type transistor comprises a total of two finger sub-devices (Iwahori, Fig. 1B).
Regarding claims 9-10, the Office reminds Applicant that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. See MPEP 2113(I). It is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. Note that applicant has the burden of proof in such cases. See MPEP 2113(II). Thus, no patentable weight will be given to those process steps which do not add structural limitations to the final product. The combination of Yu and Iwahori teaches the structure formed by the method (Yu, Fig. 31, stacked semiconductors 106, [0028], gate dielectric 180, [0062], dielectric barrier 141, [0045], n-type and p-type metal gate layers 182/184, [0071], [0076]).
Regarding claim 20, the combination of Yu and Iwahori teaches wherein the n-type transistor and the p-type transistor are arranged next to each other along a first direction, and wherein the plurality of finger sub-devices of the n-type transistor and the plurality of finger sub-devices of the p-type transistor are arranged next to each other along the first direction (Iwahori, Fig. 1B).
Regarding claim 21, the combination of Yu and Iwahori teaches wherein semiconducotrs of the plurality of stacked semiconductors are stacked above each other on the substrate along a second direction, the second direction being perpendicular to the first direction (Yu, Fig. 31; Iwahori, Fig. 1B).
Regarding claim 22, the combination of Yu and Iwahori teaches wherein the gate dielectric layer surrounds at least three side surface of the each of the plurality of stacked semiconductors (Yu, Fig. 31, 180, 182/184, [0062], [0071], [0076]; Iwahori, [0049]-[0050]).
Regarding claim 11, Yu teaches a method of manufacturing a semiconductor architecture, comprising providing a substrate, forming a plurality of stacked semiconductors on the substrate to form an n-type transistor and a p-type transistor on the substrate, wherein each of the n-type transistor and the p-type transistor comprises a plurality of finger sub-devices, and each finger sub-device of the plurality of finger sub-devices comprises the plurality of stacked semiconductors (substrate 101, [0018]; stacked semiconductors, 106, [0028]; Fig. 16A, n-type transistor 112b, p-type transistor 112a and 112c, [0055]), depositing a gate dielectric (180, [0062]), forming a dielectric layer over the plurality of finger sub-devices, etching the dielectric layer from a top and at least one side of each of the plurality of finger sub-devices, leaving a dielectric barrier extending down only one side of a subset of the stacked semiconductors (Figs. 6-11, [0044]-[0046], 141), and depositing one or more metal gate layers, wherein one or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising the dielectric barrier extending down only one side of the stacked semiconductors (Fig. 31, n-type and p-type metal gate layers 182/184, [0071], [0076]).
Yu does not explicitly teach wherein a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor.
Iwahori teaches two n-type and two p-type finger sub-devices comprising forksheet FETs, wherein one of the finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device comprising a dielectric barrier which extends down only one side only of the stacked semiconductors, a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor (Figs. 1A-1B, P11/P12/N11/N12, [0037], [0049]-[0052]; dielectric barriers not depicted but forksheet FETs are defined by the presence of a dielectric barrier contacting the side of stacked nanosheets), see annotated Fig. 1B with the locations of the dielectric barriers shown, compare with Fig. 1B of the instant application.
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hirose with Yu such that a finger sub-device of the n-type transistor which is distal from the p-type transistor comprises a second dielectric barrier extending down a side of the stacked semiconductors which is distal from the p-type transistor; and a finger sub-device of the p-type transistor which is distal from the n-type transistor comprises a third dielectric barrier extending down a side of the stacked semiconductors which is distal from the n-type transistor for the purpose of forming a standard cell comprising forksheet transistors formed according to the method of Yu (Hirose, [0037], [0035]).
Regarding claim 12, the combination of Yu and Iwahori teaches wherein the etching and depositing steps are configured to surround three sides of each fork stack device with a gate dielectric layer and an n-type metal gate layer or a p-type metal gate layer (Yu, Fig. 31, 180, 182/184, [0062], [0071], [0076]; Iwahori, [0049]-[0050]).
Regarding claim 14, the combination of Yu and Iwahori teaches wherein the etching of a finger sub-device of the n-type transistor and a finger sub-device of the p-type transistor forms the dielectric barrier which extends between the n-type transistor and the p-type transistor (Yu, Figs. 6-11, [0044]-[0046], 141).
Regarding claim 17, the combination of Yu and Iwahori teaches wherein each of the n-type transistor and the p-type transistor comprises a total of two finger sub-devices (Iwahori, Fig. 1B).
Regarding claim 18, the combination of Yu and Iwahori teaches wherein each of the finger sub-devices of the plurality of finger sub-devices includes a total of three stacked semiconductors (Yu, Fig. 31; Iwahori, Fig. 1B).
Regarding claim 19, the combination of Yu and Iwahori teaches wherein depositing the one or more metal gate layers comprises depositing an n-type metal gate layer, etching the n-type metal gate layer, and depositing a p-type metal gate layer (Yu, Figs. 26-29, n-type and p-type metal gate layers 182/184, [0070]-[0076]).
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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