DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (U.S. Patent Application Publication No. 2023/0275084).
Regarding to claim 10, Hong teaches a semiconductor structure comprising:
a diode located in a passive/diode device region (Fig. 2, element 200C) and present between two adjacent stacked nanosheet transistors (Fig. 2, [0037], lines 1-6), wherein the diode comprises a first doped semiconductor pillar of a first conductivity type (Fig. 2, element N) sandwiched between a pair of second doped semiconductor pillars of a second conductivity type that is opposite the first conductivity type (Fig. 2, elements P1/P2, first doped semiconductor N (n-type) sandwiched between pair of second doped semiconductor P1 and P2 (p-type));
a first backside contact structure contacting one of the second doped semiconductor pillars (Fig. 2, element 203);
a second contact structure contacting another of the second doped semiconductor pillars (Fig. 2, element 204-1); and
a frontside contact structure contacting the first doped semiconductor pillar (Fig. 2, element 204-2).
Hong does not disclose the second contact structure is a backside contact structure. However, it would have been an obvious matter of design choice to configure the second contact structure to be a backside contact structure, since applicant has not disclosed that backside contact solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well if the contacts to the second conductivity type materials are both located on front or back side of the device.
Regarding to claim 15, Hong teaches a frontside back-end-of-the line (BEOL) structure located on top of the two adjacent stacked nanosheet transistors (Fig. 2, elements CA).
Regarding to claim 16, Hong teaches at least one other stacked nanosheet transistor located in a logic device region that is adjacent to the passive/diode device, wherein the at least one other stacked nanosheet transistor comprises a bottom nanosheet transistor having bottom source/drain regions, and a top nanosheet transistor located above the bottom nanosheet transistor and having top source/drain regions (Fig. 2, [0037], lines 7-12).
Regarding to claim 17, Hong teaches a semiconductor structure comprising:
a bottom diode located in a passive/diode device region (Fig. 2, element P1/N) and present between two adjacent stacked nanosheet transistors (Fig. 2, [0037], lines 1-6), wherein the bottom diode comprises a first doped bottom semiconductor pillar of a first conductivity type (Fig. 2, element N, n-type) and a second doped bottom semiconductor pillar of a second conductivity type that is opposite the first conductivity type (Fig. 2, element P1, p-type), wherein the first doped bottom semiconductor pillar and the second doped bottom semiconductor pillar are in direct physical contact with each other (Fig. 2);
a top diode (Fig. 2, element P2/N), wherein the top diode comprises a first doped top semiconductor pillar of the first conductivity type (Fig. 2, element N) and a second doped top semiconductor pillar of the second conductivity type (Fig. 2, element P2), wherein the first doped top semiconductor pillar and the second doped top semiconductor pillar are in direct physical contact with each other (Fig. 2).
a first backside contact structure contacting the first doped bottom semiconductor pillar (Fig. 2, element 204-2);
a second backside contact structure contacting the second doped bottom semiconductor pillar (Fig. 2, element 204-1); and
a second frontside contact structure contacting the second doped top semiconductor pillar (Fig. 2, element 203).
Hong does not disclose the top diode spaced apart from the bottom diode and a first frontside contact structure contacting the first doped top semiconductor pillar. However, it would have been an obvious matter of design choice to space the top diode apart from the bottom diode and contact the first frontside contact structure to the first doped top semiconductor pillar, since applicant has not disclosed that separation and backside contact solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well otherwise.
Regarding to claim 18, Hong teaches the bottom diode is located laterally adjacent to a bottom nanosheet transistor of each of the two adjacent stacked nanosheet transistors, and the top diode is located laterally adjacent to a top nanosheet transistor of each of the two adjacent stacked nanosheet transistors (Fig. 2).
Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (U.S. Patent Application Publication No. 2023/0275084) in view of Bhattacharyya (U.S. Patent No. 8,125,003).
Regarding to claim 1, Hong teaches a semiconductor structure comprising:
a diode located in a passive/diode device region and present between two adjacent stacked nanosheet transistors (Fig. 1, element 100C; [0034], lines 1-3; [0037], lines 1-6), wherein the diode comprises a first doped semiconductor pillar of a first conductivity type (Fig. 1, element N, n-type) and a second doped semiconductor pillar of a second conductivity type that is opposite the first conductivity type (Fig. 1, element P, p-type),
a first backside contact structure contacting the first doped semiconductor pillar (Fig. 1, element 104); and
a second contact structure contacting the second doped semiconductor pillar (Fig. 1, element 103).
Hong does not disclose an intrinsic semiconductor pillar located laterally between the first doped semiconductor pillar and the second doped semiconductor pillar, and the second contact is a backside contact.
Bhattacharyya discloses an intrinsic semiconductor pillar located laterally between the first doped semiconductor pillar and the second doped semiconductor pillar (Fig. 22, element 2216, column 23, line 20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hong in view of Bhattacharyya to laterally locate an intrinsic semiconductor pillar between the first doped semiconductor pillar and the second doped semiconductor pillar in order to increase junction width, reducing capacitance and improve switching speed.
In the embodiment of Fig. 2, Hong discloses the contact to n-doped semiconductor is in the same side with the contact to p-doped semiconductor (Fig. 2, elements 2014-1 and 204-2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hong to locate the second contact structure on the same side with the first contact structure. As a result, second contact structure is a backside contact.
Regarding to claim 6, Hong teaches a frontside back-end-of-the-line (BEOL) structure located on top of the two adjacent stacked nanosheet transistors (Fig. 1, elements CA).
Regarding to claim 7, Hong teaches at least one other stacked nanosheet transistor located in a logic device region that is adjacent to the passive/diode device, wherein the at least one other stacked nanosheet transistor comprises a bottom nanosheet transistor having bottom source/drain regions of the first conductivity type, and a top nanosheet transistor located above the bottom nanosheet transistor and having top source/drain regions of the second conductivity type (Fig. 1, [0037], lines 7-12).
Allowable Subject Matter
Claims 2-5, 8-9, 11-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 2, the prior art fails to anticipate or render obvious the claimed limitations including “the first doped semiconductor pillar directly contacts a sidewall of a first stacked nanosheet transistor of the two adjacent stacked nanosheet transistors, and the second doped semiconductor pillar directly contacts a sidewall of a second stacked nanosheet transistor of the two adjacent stacked nanosheet transistors” in combination with the limitations recited in claim 1.
Regarding to claim 3, the prior art fails to anticipate or render obvious the claimed limitations including “the diode has a height that is substantially equally to a topmost second semiconductor channel material nanosheet of the two adjacent stacked nanosheet transistors” in combination with the limitations recited in claim 1.
Regarding to claim 4, the prior art fails to anticipate or render obvious the claimed limitations including “the first backside contact structure and the second backside contact structure are present in a first backside interlayer dielectric (ILD) layer, and the first backside metal structure and the second backside metal structure are present in a second backside ILD layer” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 4.
Regarding to claim 5, the prior art fails to anticipate or render obvious the claimed limitations including “the diode including each of the first doped semiconductor pillar, the intrinsic semiconductor pillar and the second doped semiconductor pillar lands on a surface of a shallow trench isolation structure” in combination with the limitations recited in claim 1.
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “one of the second doped semiconductor pillars directly contacts a sidewall of a first stacked nanosheet transistor of the two adjacent stacked nanosheet transistors, and another of the second doped semiconductor pillar directly contacts a sidewall of a second stacked nanosheet transistor of the two adjacent stacked nanosheet transistors” in combination with the limitations recited in claim 10.
Regarding to claim 12, the prior art fails to anticipate or render obvious the claimed limitations including “the diode has a height that is substantially equally to a topmost second semiconductor channel material nanosheet of the two adjacent stacked nanosheet transistors” in combination with the limitations recited in claim 10.
Regarding to claim 13, the prior art fails to anticipate or render obvious the claimed limitations including “the first backside contact structure and the second backside contact structure are present in a first backside interlayer dielectric (ILD) layer, and the first backside metal structure and the second backside metal structure are present in a second backside ILD layer” in combination with the limitations recited in claim 10 and the rest of limitations recited in claim 13.
Regarding to claim 14, the prior art fails to anticipate or render obvious the claimed limitations including “the diode including each of the first doped semiconductor pillar, and the pair of second doped semiconductor pillars lands on a surface of a shallow trench isolation structure” in combination with the limitations recited in claim 10.
Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “the bottom diode including each of the comprises a first doped bottom semiconductor pillar of a first conductivity type and a second doped bottom semiconductor pillar lands on a surface of a shallow trench isolation structure” in combination with the limitations recited in claim 17.
Regarding to claim 20, the prior art fails to anticipate or render obvious the claimed limitations including “the first backside contact structure and the second backside contact structure are present in a first backside interlayer dielectric (ILD) layer, and the first backside metal structure and the second backside metal structure are present in a second backside ILD layer” in combination with the limitations recited in claim 17 and the rest of limitations recited in claim 20.
Pertinent Art
For the benefits of the Applicant, US-20240332282-A1 and US-20230110825-A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references disclose the limitations of the claims expect for “a diode located in a passive/diode device region and present between two adjacent stacked nanosheet transistors.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897