DETAILED ACTION
This action is responsive to the application No. 18/531,070 filed on December 6, 2023.
Regarding the filing date, it is noted Applicant filed a German copy of the specification on December 6, 2023, and subsequently filed a specification in English on January 10, 2024. It appears Applicant provided no corresponding statement that the English translation is accurate, as required, see 35 USC 111, 37 CFR 1.52, and MPEP §§601 and 608.01.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to device claims 16-27 and 31-34, in the reply filed on May 4, 2026, is acknowledged. Claims 28-30 are withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the undercut in the device of Fig. 4, the control terminal and two power terminals, and the devices with more than one (regarding the “at least one” language, see discussion below) power conductor structure, further circuit carrier, further power conductor structure, control signal conductor structure, semiconductor switch, control terminal, spacer element, and more than three sinter layers encompassed by the “at least” claim language must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16-27 and 31-34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16 recites “at least one…”, this language including a plurality, i.e. one or more, one being the minimum number of each recited element, with respect to several, single, elements: power conductor structure, further circuit carrier, further power conductor structure, control signal conductor structure, semiconductor switch, control terminal, and spacer element. This language is also similarly used with respect to the “at least three” sinter layers. There is no disclosure of a power module with three further circuit carriers, four semiconductor switches, seven sinter layers, and three spacers in the stack, while the claims encompass such a device. Applicant does not disclose or show a plurality of any of: the power conductor structure, the further circuit carrier, the further power conductor structure, the control signal conductor structure, the semiconductor switch, the control terminal, or the spacer element (in the claimed stack). The claimed stack has exactly three sinter layers. Reciting at least three includes four or more layers in the claimed stack. There is no written description support for more than three sinter layers.
Device claim 16 is drawn to the completed device structure shown in Fig. 4 having the connection line 44, and no undercut at 46. The undercut at 46 was filled in a prior manufacturing step (Fig. 2) during a sintering process. Claims 31-34, reciting the undercut that is no longer present, are drawn to a new device structure having no written description support.
Claim 27 recites a casing completely surrounds the power module while leaving the at least one thermal interface exposed, wherein the casing has at least one recess in the region of at least one external contact terminal. The claim language contradicts itself and is not supported. Either the casing completely surrounds the power module or it does not. The bottom surface and the top surface of the power module are not completely surrounded (see Fig. 4). The power module is partially surrounded by the casing. There is no written description support for a power module completely surrounded by a casing while simultaneously not being completely surrounded by the casing.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-27 and 31-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites “at least one…”, this language including a plurality, i.e. one or more, one being the minimum number of each recited element, with respect to several, single, elements: power conductor structure, further circuit carrier, further power conductor structure, control signal conductor structure, semiconductor switch, control terminal, and spacer element. This language is also similarly used with respect to the “at least three” sinter layers. This unbounded range renders the claims indefinite as it is unclear what undisclosed devices are included or how these devices are constructed. There is no disclosure of a power module with three further circuit carriers, four semiconductor switches, seven sinter layers, and three spacers in the stack. Clearly, Applicant is not forming a device including 1000’s of each of these parts, so at least one must have some upper limit. The only device shown and described with any specificity includes exactly one power conductor structure, further circuit carrier, further power conductor structure, control signal conductor structure, semiconductor switch, control terminal, and a stack including one spacer element and exactly three sinter layers.
The claims recite “sinter layer(s)”, rendering the claims indefinite as it is unclear if this means the layers are capable of being sintered or if the layers have been sintered in a sintering process, or if the layer(s) participate in sintering in some other capacity, e.g. layers providing support or heat conduction thereby enabling other parts of the structure to be sintered. It is further unclear if the recited “sinter layer(s)” is intended to be construed as a product-by-process limitation, i.e. sintered layers formed by a sintering process (see MPEP §2113). It is further unclear if or how the claimed “sinter layers” are different in structure or composition than any other conductive layer, e.g. a solder layer. For the purpose of examination, this will simply be treated as a layer(s), regardless of a sintering process or any intent or ability to sinter.
Claim 27 recites a casing completely surrounds the power module while leaving the at least one thermal interface exposed, wherein the casing has at least one recess in the region of at least one external contact terminal. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “completely surrounds” in claim 27 is used by the claim to mean “partially surrounds,” while the accepted meaning is “to enclose something on all sides simultaneously, forming a continuous boundary.” The term is indefinite because the specification does not clearly redefine the term.
Next, claim 27 recites “the region”, lacking antecedence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-26 are rejected under 35 U.S.C. 103 as being unpatentable over Nippert et al. (US 4,710,795) in view of Ikeda et al. (US 2011/0037166) and Jeon (US 2016/0126157).
(Re Claim 16) Nippert teaches a power module for a vehicle, comprising (see Figs. 1-7 and supporting text):
a first circuit carrier, which has, on a first side, at least one power conductor structure arranged on an electrically insulating layer (Fig. 1, 2 is a direct bonded copper (DBC) substrate made of a ceramic core with metal 9/4 on both sides, col 4 line 39-col 5 line 17);
at least one further circuit carrier, which is arranged spatially parallel to the first circuit carrier and has, on a first side facing the first side of the first circuit carrier, at least one further power conductor structure arranged on an electrically insulating layer, and, on a second side facing away from the first side of the first circuit carrier, at least one control signal conductor structure arranged on the electrically insulating layer (3 is also a DBC substrate made of a ceramic core with metal 9 on both sides, col 4 line 39-col 5 line 17); and
at least one semiconductor switch, which has a semiconductor substrate with two power terminals and at least one control terminal (semiconductor component 5 is a thyristor, col 4 lines 51-65, a semiconductor thyristor is made in/on a semiconductor substrate), wherein the two power terminals (power terminals not labeled on 5 and correspond to the anode and cathode of the thyristor on the top and bottom of the chip contacting 7 for vertical current flow through the device, also see Figs. 4-7 and col 6 line 24 - col 7 line 46) of the at least one semiconductor switch and at least one spacer element (spacer 7) are arranged between the at least one power conductor structure of the first circuit carrier and the at least one further power conductor structure of the at least one further circuit carrier in a stack with at least three sinter layers (the entire device assembly is soldered together, solder not shown on switch 5, solder locations between 7 and 9 at dashed circles in Figs. 5-6, see col 3 lines 40-68, col 4 lines 51-65, col 5 line 56-col 6 line 9, col 7 line 3-58, further discussed below, there is solder between the switch 5 and the spacers 7 on both sides and between the spacers 7 and the two DBC substrates), wherein the at least one control terminal of the semiconductor switch is electrically connected via a connection line to a corresponding contact region of the at least one control signal conductor structure (wire 14 is connected to the gate at 8 and to top of 3 at 9 (G)), and wherein the connection line is arranged in a free space and overlaps portions of the stack and the at least one further circuit carrier (Fig. 1).
Nippert describes the solder connections, however does not show the actual solder layers in Fig. 1. A PHOSITA would be motivated to look to related devices to show the actual disposition of the solder layers in a power module device. Related art from Ikeda shows (e.g. see Figs. 1, 14, 15 and ¶¶37-81) how conventional solder connections are formed in a power module comprising a lower DBC substrate 10A, a first layer of solder 11, semiconductor switch 20, a second layer of solder 12, a spacer 30, a third layer of solder 13, and the upper DBC substrate 10B. Related art from Jeon also similarly teaches a conventional power module (see Fig. 2) comprising a lower DBC substrate 210, a first layer of solder 221-1, semiconductor switch 231, a second layer of solder 222-1, a spacer 251-1, a third layer of solder 223-1, and the upper DBC substrate 260. In view of Ikeda and Jeon, a PHOSITA would find it obvious to form the solder disclosed by Nippert in the locations according to Ikeda and Jeon to form a functional power module, and in doing so, the stack comprising the three sinter layers, the spacer, and the switch is formed as claimed.1
(Re Claim 17) wherein the at least one further circuit carrier is arranged at an offset from the at least one spacer element so that the free space for the connection line is formed (shown in Fig. 1).
(Re Claim 18) wherein a first sinter layer of the at least three sinter layers is formed between the at least one power conductor structure of the first circuit carrier and one of the two power terminals of the at least one semiconductor switch, wherein a second sinter layer of the at least three sinter layers is formed between the other of the two power terminals of the at least one semiconductor switch and the at least one spacer element, and wherein a third sinter layer of the at least three sinter layers is formed between the at least one spacer element and the at least one further power conductor structure of the at least one further circuit carrier (as discussed above in claim 16, Nippert discusses the solder layers but does not show the actual solder, related art from Ikeda and Jeon show the specific locations of the three layers as claimed).
(Re Claims 19-21) wherein at least one of the at least three sinter layers is applied as a sintering paste to a corresponding contact region or the other of the two power terminals; wherein the first sinter layer and the third sinter layer are each applied as a sintering paste; and wherein the second sinter layer is applied as a sinter foil (as discussed above in claim 16, Nippert discusses the solder layers but does not show the actual solder, related art from Ikeda and Jeon show the specific locations of the three layers as claimed, the process of forming the layers is immaterial).
Claims 19-21 are product-by-process claims. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed applied as a paste or foil need not be formed by the process of applying as a paste or foil. The final device structure will be the same regardless of the means for providing the layers. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
(Re Claim 22) wherein a first contact region of the at least one power conductor structure of the first circuit carrier corresponds to at least one surface of the one of the two power terminals of the at least one semiconductor switch (see Fig. 1).
(Re Claim 23) wherein a first contact region of the at least one spacer element corresponds to a surface of the other of the two power terminals of the at least one semiconductor switch (see Fig. 1).
(Re Claim 24) wherein a first contact region of the at least one further power conductor structure of the at least one further circuit carrier at least partially covers a second contact region of the at least one spacer element (see Fig. 1).
(Re Claim 25) wherein the first contact region of the at least one further power conductor structure of the at least one further circuit carrier covers 20% to 80% of the second contact region of the at least one spacer element (the contact regions are not well defined and may be arbitrarily selected to meet this limitation, for example, the contact region of the spacer may be defined as 20%-80% of the upper surface of the spacer 7 to meet this limitation, see Fig. 1).
(Re Claim 26) wherein the first circuit carrier has, on a second side, at least one conductor structure (Fig. 1: 4), which forms at least one thermal interface that can be contacted with a cooling device.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Nippert et al., Ikeda et al., and Jeon, as applied above, and further in view of Nashida et al. (US 2017/0018524).
(Re Claim 27, also see §112 rejections above) wherein a casing completely surrounds the power module while leaving the at least one thermal interface exposed, wherein the casing has at least one recess in the region of at least one external contact terminal.
Nippert is silent regarding a casing. A PHOSITA desiring to make and use Nippert’s device would be motivated to look to related art to teach suitable packaging to provide protection, thermal management, and external electrical connections. It is noted Nippert’s terminals are all formed on the top of the upper DBC substrate. Related art from Nashida teaches forming a casing 16 to surround the power module (Fig. 1) such that the bottom metal surface of the DBC at 11b remains exposed to allow a heat sink plate to contact the device. All of the electrical connections are formed through the top of the casing, compatible with Nippert’s power module design, and when the casing, e.g. epoxy resin, is applied around the terminals, a small meniscus forms around the terminals resulting in a recessed surface of the casing on the top of the module. By packaging Nippert’s module according to Nashida to provide protection, thermal management, and electrical connections, the bottom surface will remain exposed for a heat sink and the upper surface will include recesses due to the epoxy resin forming a meniscus with the protruding terminals. A PHOSITA would find it obvious to package Nippert’s power module according to Nashida to provide protection, thermal management, and external electrical connections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related power device packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
1 While “sinter layer” is presently treated as any layer, regardless of processing, e.g. solder, (also see §112 discussion above), should Applicant choose to better define the “sinter layer(s)”, related art from Nuoito (US 2023/0068223) is pertinent. Nuotio teaches (Fig. 4 and ¶¶30-34), as an alternative to solder, the 3 layers connecting the lower DBC to the switch, the switch to the spacer, and the spacer to the upper DBC substrate may be formed in a sintering process. ¶33: Advantages of sintering bonds of the present disclosure compared with soldering bonds are substantial reduction in thermal cycling fatigue resulting in improved durability of bonding layers and reduction of thermal resistance resulting in improved cooling performance.
Prosecution Insights