DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, Figs 2A-2C in the reply filed on 04/14/2026 is acknowledged. The traversal is on the ground(s) that the Species are not mutually exclusive. This is not found persuasive because the species have different configurations that can be claimed. The species of Fig. 3 have two corner insulating spacers with different heights instead of just one in Fig. 2B.
The species of Fig. 7 the have different inner insulating spacers 654S from ones in Fig. 2A. The species claims are rejoined when the independent claim is generic to all species.
Different features include different fields of search, which constitutes a search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claims 6, 11-13, and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/14/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guler et. al., U.S. Pat. Pub. 2022/0393013, hereafter Guler.
Regarding claim 1, Guler discloses (Figs 1, 2A-2B) an integrated circuit device comprising:
a plurality of fin-type active regions [104] extending in a first lateral direction on a substrate [102], the plurality of fin-type active regions being apart from each other in a second lateral direction, the second lateral direction intersecting with the first lateral direction (Fig 1A shows fins [104] and gates [124] orthogonal to each other and a plurality of gate cuts [122]);
a device isolation film [105] covering sidewalls of each of the plurality of fin-type active regions [104];
a gate line [124] extending in the second lateral direction on the plurality of fin- type active regions [104] and the device isolation film [105];
a plurality of nanosheet stacks (a stack of nanosheets [108] above each fin [104]) on a fin top surface of each of the plurality of fin-type active regions [104], each nanosheet stack comprising at least one nanosheet [108], and each nanosheet stack being surrounded by the gate line [124];
a gate cut [118] insulating portion [122] on the device isolation film [105], the gate cut insulating portion facing an end sidewall of the gate line [124] in the second lateral direction; and
a corner insulating spacer [120A] between a first nanosheet stack and the gate cut insulating portion [122] and between the device isolation film [105] and the gate line [124], the first nanosheet stack being selected from the plurality of nanosheet stacks and being closest to the gate cut [118A] insulating portion [122] in the second lateral direction (see Fig. 2A for plan view).
Regarding claim 2, Guler further discloses (Figs 1, 2) wherein the corner insulating spacer [120A] is in contact with each of the gate cut insulating portion [122] and the device isolation film [105].
Regarding claim 3, Guler further discloses (Figs. 1D, 2A) wherein, in the second lateral direction, a first distance between the first nanosheet stack (stack of [108]) and the gate cut insulating portion [122] is less than a distance between two adjacent ones of the plurality of nanosheet stacks (stacks of [108], see Fig. 1D).
Regarding claim 5, Guler further discloses further comprising a gate dielectric film [112] surrounding the gate line [124],
wherein the gate dielectric film [112] is between the gate line [124] and the corner insulating spacer [120A] and between the gate line [124] and the gate cut insulating portion [122] and device isolation [105].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Guler et. al., U.S. Pat. Pub. 2022/0393013, hereafter Guler in view of Chen et. al., U.S. Pat. Pub. 2021/0359109, hereafter Chen
Regarding claim 4, Guler discloses everything as applied above. Guler fails to explicitly disclose
wherein a first vertical level of an uppermost portion of the corner insulating spacer, which is farthest from the substrate, is closer to the substrate than a second vertical level of the fin top surface of each of the plurality of fin-type active regions (since the corner portion [120A] of Figs 1D and 2A of Guler extends all the way to the top of the gate cut).
However, Chen discloses (Fig. 18C) corner insulating spacers [94] only located near the corners, therefore making this limitation obvious over the combination of Guler and Chen (when the corner insulating spacer [120A] of Guler is only present near the corner of the gate cut insulating portion [122] and device isolation [105], the fin [104] will extend above the corner insulating spacer)
It would have been obvious to one of ordinary skill in the art prior to effective date of the instant application to modify the corner layer of Guler with the teachings of corner portions of Chen because Chen teaches (par. [0085]) that additional separation provided by the corner spacers can reduce parasitic capacitance between the gate stack and the epitaxial source/drain regions, which can improve high-speed performance of the device.
Regarding claim 10, Guler discloses everything as applied above. Guler fails to explicitly disclose
wherein a top surface of the corner insulating spacer, which faces the gate line, has a concave shape toward the gate line.
However, Chen discloses (Figs 17, 23B) wherein a top surface [95] of the corner insulating spacer [94], which faces the gate line [90], has a concave shape (Fig. 17) toward the gate line.
It would have been obvious to one of ordinary skill in the art prior to effective date of the instant application to modify the corner layer of Guler with the teachings of corner portions of Chen because Chen teaches (par. [0085]) that additional separation provided by the corner spacers can reduce parasitic capacitance between the gate stack and the epitaxial source/drain regions, which can improve high-speed performance of the device.
Claims 7-9, 14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guler et. al., U.S. Pat. Pub. 2022/0393013, hereafter Guler, in view of Guler et. al., U.S. Pat. Pub. 2023/0317787, hereafter ’87.
Regarding claim 7, Guler discloses everything as applied above. Guler fails to explicitly disclose
further comprising a pair of inner insulating spacers in a first space between one fin-type active region selected from the plurality of fin-type active regions and the at least one nanosheet,
wherein the pair of inner insulating spacers cover both sidewalls of a sub-gate portion filling the first space of the gate line, and
wherein at least some of the pair of inner insulating spacers comprise a same material as a constituent material of the corner insulating spacer.
However, ’87 discloses (Fig.1A, 1E) further comprising a pair of inner insulating spacers [120A] in a first space between one fin-type active region [104] selected from the plurality of fin-type active regions and the at least one nanosheet [112], wherein the pair of inner insulating spacers [130] (contacting source/drain [128] and gates [142A]) cover both sidewalls of a sub-gate portion [142A] filling the first space of the gate line.
The limitation “wherein at least some of the pair of inner insulating spacers comprise a same
material as a constituent material of the corner insulating spacer” is obvious over the combination of
references because the selection of a known material based on its suitability for its intended use
supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325
U.S. 327, 65 USPQ 297 (1945).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application for the corner insulating spacer and the inner insulating spacers because such a selection simplifies manufacturing.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify Guler with the teachings of ’87, because these are similar devices and ’87 teaches (par. [0001]-[0004]) that it is necessary to optimize performance of each device including optimizing trade-off between feature size and spacing between features.
Regarding claim 8, Guler in view of ’87 discloses everything as applied above. ’87 further discloses (Figs 1A, 1E) further comprising a source/drain region [128] in contact with a selected one of the pair of inner insulating spacers [130], wherein the source/drain region [128] comprises a protrusion that is convex toward the sub-gate portion [142A] (See Fig. 1A, 1E).
Regarding claim 9 , Guler in view of ’87 discloses everything as applied above. ’87 further discloses (Figs 1A, 1E)
further comprising a source/drain region [128] in contact with a selected one of the pair of inner insulating spacers [130],
wherein the selected inner insulating spacer [130] comprises a first sidewall facing the gate line [140A] and a second sidewall facing the source/drain region [128], and
wherein the first sidewall and the second sidewall are asymmetrical with each other (Fig. 1A,1E).
Regarding claim 14, Guler discloses (Figs 1, 2A-2B) an integrated circuit device comprising:
a fin-type active region [104] extending in a first lateral direction on a substrate [102];
a device isolation film [105] covering sidewalls of the fin-type active region [104];
a plurality of nanosheets [108] on a fin top surface of the fin-type active region [104], the plurality of nanosheets overlapping each other in a vertical direction;
a gate line [124] extending in a second lateral direction on the fin-type active region [104] and the device isolation film [105], the gate line [124] surrounding the plurality of nanosheets [108], the second lateral direction intersecting the first lateral direction;
a gate cut [118] insulating portion [122] on the device isolation film [105], the gate cut insulating portion facing an end sidewall of the gate line [124] in the second lateral direction; and
a corner insulating spacer [120A] between the plurality of nanosheets [108] and the gate cut insulating portion [122] and between the device isolation film [105] and the gate line [124].
Guler fails to explicitly disclose further comprising:
a source/drain region on the fin-type active region, the source/drain region being in contact with the plurality of nanosheets;
a plurality of inner insulating spacers respectively one-by-one between the plurality of nanosheets, each inner insulating spacer being between the source/drain region and the gate line in the first lateral direction,
at least some of the plurality of inner insulating spacers comprising a same material as a constituent material of the corner insulating spacer.
However, ’87 discloses (Figs 1A, 1E) further comprising:
a source/drain region [128] on the fin-type active region [104], the source/drain region being in contact with the plurality of nanosheets [112];
a plurality of inner insulating spacers [130] respectively one-by-one between the plurality of nanosheets [112], each inner insulating spacer being between the source/drain region [128] and the gate line [140A] in the first lateral direction,
The limitation “wherein at least some of the pair of inner insulating spacers comprise a same
material as a constituent material of the corner insulating spacer” is obvious over the combination of
references because the selection of a known material based on its suitability for its intended use
supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325
U.S. 327, 65 USPQ 297 (1945).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application for the corner insulating spacer and the inner insulating spacers because such a selection simplifies manufacturing.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify Guler with the teachings of ’87, because these are similar devices and ’87 teaches (par. [0001]-[0004]) that it is necessary to optimize performance of each device including optimizing trade-off between feature size and spacing between features.
Regarding claim 19, Guber in view of ’87 discloses everything as applied above. ’87 further discloses (Figs 1A, 1E)
wherein each of the plurality of inner insulating spacers [130] comprises a first sidewall facing the gate line [140] and a second sidewall facing the source/drain region [128], and
the first sidewall is asymmetrical with the second sidewall (see Fig. 1E).
Regarding claim 20, Guler discloses (Figs 1, 2A-2B) an integrated circuit device comprising:
a plurality of fin-type active regions [104] extending in a first lateral direction on a substrate [102];
a device isolation film [105] covering sidewalls of each of the plurality of fin-type active regions [104];
a plurality of nanosheet stacks (a stack of nanosheets [108] above each fin [104]) on a fin top surface of each of the plurality of fin-type active regions [104], each nanosheet stack comprising a plurality of nanosheets [108];
a gate line [124] extending long in a second lateral direction on the plurality of fin-type active regions [104] and the device isolation film [105], the gate line [124] surrounding a first nanosheet stack, which is selected from the plurality of nanosheet stacks, the second lateral direction intersecting with the first lateral direction;
a gate cut [118] insulating portion [122] adjacent to the first nanosheet stack (a stack of [108])
on the device isolation film [105], the gate cut insulating portion facing an end sidewall of the gate line [124] in the second lateral direction; and
a corner insulating spacer [120A] between a first nanosheet stack and the gate cut insulating portion [122] and between the device isolation film [105] and the gate line [124], the first nanosheet stack being selected from the plurality of nanosheet stacks and being closest to the gate cut [118A] insulating portion [122] in the second lateral direction (see Fig. 2A for plan view).
Guber fails to explicitly disclose
a source/drain region on the plurality of fin-type active regions, the source/drain region being in contact with the first nanosheet stack;
a plurality of inner insulating spacers respectively one-by-one between the plurality of nanosheets included in the first nanosheet stack, each inner insulating spacer being in contact with the source/drain region,
wherein each of the corner insulating spacer and the plurality of inner insulating spacers comprises silicon nitride, silicon oxide, silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), fluorinated silicon oxide (SiOF), hydrogenated silicon oxycarbide (SiOCH), or a combination thereof, and
at least some of the plurality of inner insulating spacers comprise a same material as a constituent material of the corner insulating spacer.
However, ’87 discloses (Figs 1A,1E)
a source/drain region [128] on the plurality of fin-type active regions [104], the source/drain region being in contact with the first nanosheet stack (stack of [112]);
a plurality of inner insulating spacers [130] respectively one-by-one between the plurality of nanosheets [112] included in the first nanosheet stack, each inner insulating spacer [130] being in contact with the source/drain region [128].
The limitation “wherein at least some of the pair of inner insulating spacers comprise a same
material as a constituent material of the corner insulating spacer” is obvious over the combination of
references because the selection of a known material based on its suitability for its intended use
supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325
U.S. 327, 65 USPQ 297 (1945).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application for the corner insulating spacer and the inner insulating spacers because such a selection simplifies manufacturing.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify Guler with the teachings of ’87, because these are similar devices and ’87 teaches (par. [0001]-[0004]) that it is necessary to optimize performance of each device including optimizing trade-off between feature size and spacing between features.
The limitation “wherein each of the corner insulating spacer and the plurality of inner insulating spacers comprises silicon nitride, silicon oxide, silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), fluorinated silicon oxide (SiOF), hydrogenated silicon oxycarbide (SiOCH), or a combination thereof” is further disclosed by the combination of references, since Guler discloses (par. [0030]) silicon nitride for the corner insulating spacer, while ’87 discloses (par. [0110]) some of the materials above including silicon oxide, silicon nitride, carbon-doped silicon nitride, and silicon oxynitride.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Guler et. al., U.S. Pat. Pub. 2022/0393013, hereafter Guler in view of Guler et. al., U.S. Pat. Pub. 2023/0317787, hereafter ’87, and further in view of Chen et. al., U.S. Pat. Pub. 2021/0359109, hereafter Chen.
Regarding claim 15, Guler in view of ’87 discloses everything as applied above. Guler in view of ’87 fails to explicitly disclose
wherein a first vertical level of an uppermost portion of the corner insulating spacer, which is farthest from the substrate, is closer to the substrate than a second vertical level of the fin top surface of the fin-type active region.
However, Chen discloses (Fig. 18C) corner insulating spacers [94] only located near the corners, therefore making this limitation obvious over the combination of Guler, ’87, and Chen (when the corner insulating spacer [120A] of Guler is only present near the corner of the gate cut insulating portion [122] and device isolation [105], the fin [104] will extend above the corner insulating spacer)
It would have been obvious to one of ordinary skill in the art prior to effective date of the instant application to modify the corner layer of Guler with the teachings of corner portions of Chen because Chen teaches (par. [0085]) that additional separation provided by the corner spacers can reduce parasitic capacitance between the gate stack and the epitaxial source/drain regions, which can improve high-speed performance of the device.
Allowable Subject Matter
Claims 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16, the prior art of record fails to explicitly disclose or make obvious wherein the corner insulating spacer comprises a portion of which a thickness in the vertical direction increases toward the gate cut insulating portion in the second lateral direction.
Regarding claim 18, the prior art of record fails to explicitly disclose or make obvious further comprising a source/drain contact adjacent to each of the gate cut insulating portion and the gate line, the source/drain contact being connected to the source/drain region, wherein the corner insulating spacer and the source/drain contact overlap each other in the first lateral direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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