DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/16/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ELECTRONIC DEVICE COMPRISING MIXED MATERIAL LAYER AND ELECTRONIC APPATATUS INCLUDING THE SAME
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 11, 14-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Prasad et al. US PGPub. 2021/0074727
Regarding claim 1, Prasad teaches an electronic device (fig. 13A and 9B) comprising: a conductive material layer (60, fig. 9B and 13A) [0145]; a mixed material layer (54L/54C, fig. 13A) [0137] covering the conductive material layer (60) and comprising a mixture of an orthorhombic crystal phase [0138] and a tetragonal crystal phase [0138] such that a ferroelectric material [0138] and an anti-ferroelectric material [0138] coexist in the mixed material layer (54L), wherein a proportion of the orthorhombic crystal phase in the mixed material layer (54L) is between about 35% and about 65% (50%, [0138]); and an electrode layer (46, fig. 13A) [0172]) covering the mixed material layer (54L) (Prasad et al., fig. 13A). Regarding claim 2, Prasad teaches the electronic device of claim 1, wherein the mixed material layer (54L/54C) comprises an oxide comprising Hf.sub.1-xA.sub.xO.sub.2 (x≤0.5), and A comprises at least one of Al, Si, Zr, Y, La, Gd, and Sr (Hf1-xZrxO2, 0.3 ≤ x ≤ 0.7, [0138]) (Prasad et al., [0138])
Regarding claim 3, Prasad teaches the electronic device of claim 1, wherein the mixed material layer (54L/54C) comprises Hf.sub.1-xZr.sub.xO.sub.2 (x≤0.5) (Hf1-xZrxO2, 0.3 ≤ x ≤ 0.7, [0138]) (Prasad et al., [0138])
Regarding claim 11, Prasad teaches the electronic device of claim 1, wherein the electronic device (fig. 13A) comprises a transistor [0004], the conductive material layer (60) comprises a channel [0145], and the electrode layer (46) comprises a gate electrode [0172]) (Prasad et al., fig. 13A). Regarding claim 14, Prasad teaches the electronic device of claim 11, further comprising: a stack structure (46+32, fig. 13A) including a plurality of the gate electrode (46, fig. 13A) [0172] alternately stacked in a vertical direction (z direction, fig. 13A) with a plurality of insulating layers (32, fig. 13A) [0113]; a plurality of channel holes (49, fig. 4A) [0129] penetrating the stack structure (46+32) in the vertical direction; and a plurality of memory cell strings (58, fig. 13A) [0149] in the plurality of channel holes (49), the plurality of memory cell strings (58) each including the mixed material layer (54L, fig. 9B) [0137] and the conductive material layer (60, fig. 9B) [0145] concentrically arranged inside the plurality of channel holes (49), wherein the plurality of memory cell strings (58) are two-dimensionally arranged (fig. 13B) (Prasad et al., fig. 9B and 13A-B). Regarding claim 15, Prasad teaches an electronic apparatus [0004] comprising at least one electronic device (fig. 13A), wherein the at least one electronic device (fig. 13A) comprises: a conductive material layer (60, fig. 9B and 13A) [0145]; a mixed material layer (54L/54C, fig. 13A) [0137] covering the conductive material layer (60) and comprising a mixture of an orthorhombic crystal phase [0138] and a tetragonal crystal phase [0138] such that a ferroelectric material [0138] and an anti-ferroelectric material [0138] coexist in the mixed material layer (54L), wherein a proportion of the orthorhombic crystal phase in the mixed material layer (54L) is between about 35% and about 65% (50%, [0138]); and an electrode layer (46, fig. 13A) [0172]) covering the mixed material layer (54L) (Prasad et al., fig. 13A). Regarding claim 20, Prasad teaches the electronic apparatus of claim 15, wherein the electronic device (fig. 13A) comprises a transistor [0004], the conductive material layer (60) comprises a channel [0145], the electrode layer (46) comprises a gate electrode [0172], and wherein the electronic device (fig. 13A) further comprises a stack structure (46+32, fig. 13A) including a plurality of the gate electrode (46, fig. 13A) [0172] alternately stacked in a vertical direction (z direction, fig. 13A) with a plurality of insulating layers (32, fig. 13A) [0113]; a plurality of channel holes (49, fig. 4A) [0129] penetrating the stack structure (46+32) in the vertical direction; and a plurality of memory cell strings (58, fig. 13A) [0149] in the plurality of channel holes (49), the plurality of memory cell strings (58) each including the mixed material layer (54L, fig. 9B) [0137] and the conductive material layer (60, fig. 9B) [0145] concentrically arranged inside the plurality of channel holes (49), wherein the plurality of memory cell strings (58) are two-dimensionally arranged (fig. 13B) (Prasad et al., fig. 9B and 13A-B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-13, 15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US PGPub. 2022/0359762. Regarding claim 1, Chen teaches an electronic device (100, fig. 1) [0021] comprising: a conductive material layer (110c, fig. 1) [0022]-[0023]; a mixed material layer (140, fig. 1) [0025] covering the conductive material layer (110c) and comprising a mixture of an orthorhombic crystal phase [0027] and a tetragonal crystal phase [0027] such that a ferroelectric material [0026] and an anti-ferroelectric material [0026] coexist in the mixed material layer (140), wherein a proportion of the orthorhombic crystal phase in the mixed material layer is between about 10% and about 90% (1/10 to 10:1 [0027] is interpreted as ~10% to ~90%); and an electrode layer (150, fig. 1) [0025] covering the mixed material layer (140). The channel layer (110c) is considered a conductive layer because it is made of the same semiconductor materials (Si or Ge or SiGe, [0022]) as that of the invention that is considered as a conductive material (see [0058] of the specification of the instant application). But Chen fails to explicitly teach wherein a proportion of the orthorhombic crystal phase in the mixed material layer is between about 35% and about 65%. However, since Chen teaches wherein a proportion of the orthorhombic crystal phase in the mixed material layer is between about 10% and about 90% (1/10 to 10:1 [0027] is interpreted as ~10% to ~90%), at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use proportion of the orthorhombic crystal phase in the mixed material layer in the range as claimed in order to produce small remnant polarization, reduced onset voltage and non-hysteresis (Chen et al., [0026]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 2, Chen teaches the electronic device of claim 1, wherein the mixed material layer (140) comprises an oxide comprising Hf.sub.1-xA.sub.xO.sub.2 (x≤0.5), and A comprises at least one of Al, Si, Zr, Y, La, Gd, and Sr (Hf1-xZrxO2, wherein x is ~0.5-~0.99, [0026]; x is 0.5 in fig. 2, [0031]) (Chen et al., [0026], [0031]).
Regarding claim 3, Chen teaches the electronic device of claim 1, wherein the mixed material layer (140) comprises Hf.sub.1-xZr.sub.xO.sub.2 (x≤0.5) (Hf1-xZrxO2, wherein x is ~0.5-~0.99, [0026]; x is 0.5 in fig. 2, [0031]) (Chen et al., [0026], [0031]).
Regarding claim 4, Chen teaches the electronic device of claim 1, wherein the mixed material layer (140) is a single layer (Chen et al., fig. 1, [0027]).
Regarding claim 8, Chen teaches the electronic device of claim 1, wherein the mixed material layer (140) has a thickness of about 0.1 nm to about 20 nm (10nm, [0025]) (Chen et al., fig. 1, [0025]).
Regarding claim 9, Chen teaches the electronic device of claim 1, wherein crystallization of the mixed material layer (140) is obtained by performing a heat treatment (annealing, [0032]) but fails to specify the heat treatment before forming the electrode layer or by performing heat treatments before and after the forming of the electrode layer. However, the process limitations “by performing a heat treatment before … or by performing heat treatments before and after …” in claim 9, do not carry weight in a claim drawn to structure. See MPEP 2113. Furthermore, the recited process limitation is not considered to impart distinctive structural characteristics to the final product.
Regarding claim 10, Chen teaches the electronic device of claim 1, further comprising: a dielectric layer (130, fig. 1) [0024] between the mixed material layer (140) and at least one of the conductive material layer (110c) and the electrode layer (Chen et al., fig. 1, [0024]).
Regarding claim 11, Chen teaches the electronic device of claim 1, wherein the electronic device (100, fi. 1 or fig. 36, [0069]) comprises a transistor (NC-FET, [0021], [0069]), the conductive material layer (110c of fig. 1 or 322 of fig. 36, [0071]) comprises a channel [0023], [0071], and the electrode layer (150 of fig. 1 or 380 of fig. 36, [0080]) comprises a gate electrode [0025], [0080] (Chen et al., fig. 36). Regarding claim 12, Chen teaches the electronic device of claim 11, further comprising: a substrate (310, fig. 36) [0070], wherein the channel (322, fig. 36) [0071] is at least one of spaced apart from an upper surface of the substrate (310) and extends in a first direction (x direction, from left to right, fig. 36), or comprises a plurality of channel elements spaced apart from each other in a second direction different from the first direction (Chen et al., fig. 36). Regarding claim 13, Chen teaches the electronic device of claim 12, wherein the channel (322) comprises the plurality of channel elements (322, fig. 36) [007], the mixed material layer (370, fig. 36) is included in a plurality of mixed material layers (370) surrounding [0080] the plurality of channel elements (322), respectively, and the gate electrode (380) protrudes from the upper surface of the substrate (310/310P, fig. 36) to surround the plurality of mixed material layers (370) (Chen et al., fig, 34-36).
Regarding claim 15, Chen teaches an electronic apparatus (integrated circuit device, [0018]) comprising at least one electronic device (NC-FET, [0018], [0069]), wherein the at least one electronic device (100, NC-FET, fig. 1 or fig. 36) [0021], [0069] comprises: a conductive material layer (110c, fig. 1 or 322, fig. 36) [0022]-[0023], [0071]; a mixed material layer (140, fig. 1, [0025] or 370, fig. 36, [0080] covering the conductive material layer (110c/370) and comprising a mixture of an orthorhombic crystal phase [0027] and a tetragonal crystal phase [0027] such that a ferroelectric material [0026] and an anti-ferroelectric material [0026] coexist in the mixed material layer (140/370), wherein a proportion of the orthorhombic crystal phase in the mixed material layer is between about 10% and about 90% (1/10 to 10:1 [0027] is interpreted as ~10% to ~90%); and an electrode layer (150, fig. 1, [0025] or 380, fig. 36, [0080]) covering the mixed material layer (140/370). The channel layer (110c) is considered a conductive layer because it is made of the same semiconductor materials (Si or Ge or SiGe, [0022]) as that of the invention that is considered as a conductive material (see [0058] of the specification of the instant application). But Chen fails to explicitly teach wherein a proportion of the orthorhombic crystal phase in the mixed material layer is between about 35% and about 65%. However, since Chen teaches wherein a proportion of the orthorhombic crystal phase in the mixed material layer is between about 10% and about 90% (1/10 to 10:1 [0027] is interpreted as ~10% to ~90%), at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use proportion of the orthorhombic crystal phase in the mixed material layer in the range as claimed in order to produce small remnant polarization, reduced onset voltage and non-hysteresis (Chen et al., [0026]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 18, Chen teaches the electronic apparatus of claim 15, wherein the electronic device (fig. 36) comprises a transistor (NC-FET, fig. 36) [0069], the conductive material layer (322) comprises a channel [0071], the electrode layer (380) comprises a gate electrode [0080], the electronic device (fig. 36) further comprises a substrate (310, fig. 36) [0070], and the channel (322) is at least one of spaced apart from an upper surface of the substrate (310) and extends in a first direction (x direction, from left to right, fig. 36), or comprises a plurality of channel elements spaced apart from each other in a second direction different from the first direction (Chen et al., fig. 36).
Regarding claim 19, Chen teaches the electronic apparatus of claim 18,
wherein the channel (322) comprises the plurality of channel elements (322, fig. 36) [007], the mixed material layer (370, fig. 36) is included in a plurality of mixed material layers (370) surrounding [0080] the plurality of channel elements (322), respectively, and the gate electrode (380) protrudes from the upper surface of the substrate (310/310P, fig. 36) to surround the plurality of mixed material layers (370) (Chen et al., fig, 34-36).
Claims 5-7 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US PGPub. 2022/0359762 as applied to claim 1 above, and further in view of Heo et al. US PGPub. 2021/0359101. Regarding claim 5, Chen teaches the electronic device of claim 1, wherein the orthorhombic crystal phase has ferroelectricity [0027], the tetragonal crystal phase has anti-ferroelectricity [0027] but fails to teach wherein the mixed material layer (140) includes one to three energy barrier regions. However, Heo teaches an electronic device (D10, fig. 1) [0046] wherein the mixed material layer (200, fig. 1) [0052] includes one to three energy barrier regions (fig. 6B, [0054]) (Heo et al., fig. 1 and 6B, [0056]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the mixed material layer of Chen with the mixed material layer of Heo having one to three energy barrier regions because such material is well known in the art and art recognized and suitable for the intended purpose of eliminating hysteresis (Heo et al., [0056]) (see MPEP 2144.07).
Regarding claim 6, Chen does not teach the electronic device of claim 1, wherein the mixed material layer (140) is configured to have two or three S-curves in a polarization-electric field relationship. However, Heo teaches an electronic device (D10, fig. 1) [0046] wherein the mixed material layer (200, fig. 1) [0052] is configured to have two or three S-curves in a polarization-electric field relationship (fig. 6A, [0056]) (Heo et al., fig. 1 and 6A, [0056]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the mixed material layer of Chen with the mixed material layer of Heo having two or three s-curves in a polarization-electric field relationship because such material is well known in the art and art recognized and suitable for the intended purpose of eliminating hysteresis (Heo et al., [0056]) (see MPEP 2144.07). Regarding claim 7, Chen teaches the electronic device of claim 1, wherein the mixed material layer (140) exhibits negative capacitance [0025] but fails to disclose that the negative capacitance is within an electric field range of about −10 MV/cm to about +10 MV/cm. However, Heo teaches an electronic device (D10, fig. 1) [0046] wherein the mixed material layer (200, fig. 1) [0052] exhibits negative capacitance ins a specific operating region (Heo et al., [0053]). Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to combine the teaching of Chen with that of Heo such that the mixed material layer exhibit negative capacitance in the electric field range as claimed in order to lower hysteresis, improve capacitance and subthreshold swing values in the electronic device (Heo et al., [0153]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Regarding claim 16, Chen teaches the electronic apparatus of claim 15, wherein the mixed material layer (140) is a single layer (fig. 1) comprising Hf.sub.1-xA.sub.xO.sub.2 (x≤0.5), A comprises at least one of Al, Si, Zr, Y, La, Gd, and Sr (Hf1-xZrxO2, wherein x is ~0.5-~0.99, [0026]; x is 0.5 in fig. 2, [0031]) (Chen et al., [0026], [0031]). But Chen fails to teach wherein the mixed material layer (140) includes one to three energy barrier regions. However, Heo teaches an electronic device (D10, fig. 1) [0046] wherein the mixed material layer (200, fig. 1) [0052] includes one to three energy barrier regions (fig. 6B, [0054]) (Heo et al., fig. 1 and 6B, [0056]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the mixed material layer of Chen with the mixed material layer of Heo having one to three energy barrier regions because such material is well known in the art and art recognized and suitable for the intended purpose of eliminating hysteresis (Heo et al., [0056]) (see MPEP 2144.07).
Regarding claim 17, Chen teaches the electronic apparatus of claim 15, wherein the mixed material layer (140) is a single layer containing Hf.sub.1-xZr.sub.xO.sub.2 (x≤0.5) (Hf1-xZrxO2, wherein x is ~0.5-~0.99, [0026]; x is 0.5 in fig. 2, [0031]) (Chen et al., [0026], [0031]) but fails to teach wherein the mixed material layer (140) includes one to three energy barrier regions.
However, Heo teaches an electronic device (D10, fig. 1) [0046] wherein the mixed material layer (200, fig. 1) [0052] includes one to three energy barrier regions (fig. 6B, [0054]) (Heo et al., fig. 1 and 6B, [0056]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the mixed material layer of Chen with the mixed material layer of Heo having one to three energy barrier regions because such material is well known in the art and art recognized and suitable for the intended purpose of eliminating hysteresis (Heo et al., [0056]) (see MPEP 2144.07).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Heo et al. US PGPub. 2020/0303385 (fig. 1) and Heo et al. US. PGPub. 2020/0055134 (fig. 1) teaches an electronic device comprising a mixed material layer with ferroelectric and anti-ferroelectric materials.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892