DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species A2 (allegedly claims 1-20) in the reply filed on 03/30/2026 is acknowledged.
The traversal is on the ground(s) that “Species A2, A3, A4, A7, and A8 can be examined together with little examination burden”. (The Examiner notes that even if she agreed to this assertion, there exist claims drawn to Species A5 and A6 in the claim set and yet, Applicant has alleged that all claims 1-20 should be examined.)
Applicant argues Figs. 3 and 4 “only modify an offset position”; however, Applicant has not admitted that such modifications are obvious variants of each other. Should Applicant clearly admit that the identified species are obvious variants of each other, the Examiner will gladly withdraw the restriction. As it stands; however, it appears that these modifications are separate inventions and would provide an examination burden at least because the prior art applicable to one species would not likely be applicable to the other species; that is, separate references would likely be required to be found for each individual species which would likely require separate search strategies.
Applicant argues Figs. 7 and 8 “only remove layers of connection terminals”; however, once again, Applicant has not admitted that such removal is an obvious variant. Should Applicant clearly admit that the identified species are obvious variants of each other, the Examiner will gladly withdraw the restriction. As it stands; however, it appears that these modifications are separate inventions and would provide an examination burden at least because the prior art applicable to one species would not likely be applicable to the other species; that is, separate references would likely be required to be found for each individual species which would likely require separate search strategies (the classification for bumps between chips (H10W90/722) is separate from the classification of direct bonded pads between chips (H10W90/792).
As always, upon the allowance of a generic claim, applicant will be entitled to consideration of claims to additional species which depend from or otherwise require all the limitations of an allowable generic claim as provided by 37 CFR 1.141.
The requirement is still deemed proper and is therefore made FINAL.
Furthermore, claims 4-7, 10-15, and 19-20 are drawn to non-elected species and are hereby withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/06/2023 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanie et al. (US Pub. 2010/0171209).
Regarding independent claim 1, Tanie teaches a semiconductor package (Figs. 1A, 1B; para. 0038+) comprising:
a base chip (1d) comprising a top surface extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction (Figs. 1A, 1B);
a semiconductor chip stack (1c, 1b, 1a) comprising a first semiconductor chip (1c) and a second semiconductor chip (1b) which are sequentially stacked on the base chip in a vertical direction and are aligned on respective sides in the vertical direction (Fig. 1B; para. 0039);
first through vias penetrating the base chip and spaced apart from each other in the first horizontal direction (Fig. 1B, where going forward the vias of the base chip (1d) will be considered 1d_v1, 1d_v2, 1d_v3, and 1d_v4 going from left to right);
second through vias penetrating the first semiconductor chip and spaced apart from each other in the first horizontal direction (Fig. 1B, where going forward the vias of the first chip (1c) will be considered 1c_v1, 1c_v2, 1c_v3, and 1c_v4 going from left to right);
third through vias penetrating the second semiconductor chip and spaced apart from each other in the first horizontal direction (Fig. 1B, where going forward the vias of the second chip (1b) will be considered 1b_v1, 1b_v2 going from left to right); and
first connection pads contacting the first through vias (Fig. 1B; unlabeled bonding pads on either the top or bottom surface of chip (1d));
second connection pads contacting the second through vias (Fig. 1B; unlabeled bonding pads on either the top or bottom surface of chip (1c)); and
third connection pads contacting the third through vias (Fig. 1B; unlabeled bonding pads on either the top or bottom surface of chip (1b)),
wherein at least one of the first through vias is offset from at least one of the second through vias in the vertical direction (Fig. 1B; for example, 1d_v1 is offset from 1c_v2),
wherein at least one of the first through vias is aligned with at least one of the second through vias in the vertical direction (Fig. 1B; for example, 1d_v1 is aligned with 1c_v1),
wherein at least one of the second through vias is offset from at least one of the third through vias in the vertical direction (Fig. 1B; for example, 1c_v1 is offset from 1b_v2), and
wherein at least one of the second through vias is aligned with at least one of the third through vias in the vertical direction (Fig. 1B; for example, 1c_v1 is aligned with 1b_v1).
Re claim 2, Tanie teaches wherein a first distance, in the first horizontal direction, between two adjacent first through vias of the first through vias is different from a second distance, in the first horizontal direction, between two adjacent second through vias of the second through vias (Fig. 1B; for example, the distance between 1d_v1 and 1d_v2 is different from the distance between 1c_v1 and 1c_v2).
Re claim 3, Tanie teaches wherein a first distance, in the first horizontal direction, between two adjacent second through vias of the second through vias is different from a second distance, in the first horizontal direction, between two adjacent third through vias of the third through vias (Fig. 1B; for example, the distance between 1c_v1 and 1c_v2 is different from the distance between 1b_v1 and 1b_v2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 9, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tanie et al. (US Pub. 2012/0171209) in view of Egawa (US Pub. 2006/0202347).
Re claims 8 and 9, Tanie is silent with respect to a mold layer and underfill layers.
Egawa teaches a semiconductor package (Fig. 2) including a mold layer (61; para. 0061) at least partially covering a base chip (bottommost chip 2), a first semiconductor chip (another 2), and a second semiconductor chip (still another 2), on the top surface of the base chip, a first underfill material layer (24) between the mold layer and the first semiconductor chip; and a second underfill material layer (another 24) between the first semiconductor chip and the second semiconductor chip, wherein the first underfill material layer and the second underfill material layer are non- conductive (para. 0060).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the mold layer and the underfill layers as taught by Egawa within the device of Tanie to arrive at the claimed invention for the purpose of providing protection to the device of Tanie (Egawa para. 0060-0061).
Regarding independent claim 16, Tanie teaches a semiconductor package (Figs. 1A, 1B; para. 0038+) comprising:
a base chip (1d) comprising a top surface extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction (Figs. 1A, 1B);
a semiconductor chip stack (1c, 1b, 1a) comprising a first semiconductor chip (1c) and a second semiconductor chip (1b) which are sequentially stacked on the base chip in a vertical direction and are aligned on respective sides in the vertical direction (Fig. 1B; para. 0039);
first through vias penetrating the base chip and spaced apart from each other in the first horizontal direction (Fig. 1B, where going forward the vias of the base chip (1d) will be considered 1d_v1, 1d_v2, 1d_v3, and 1d_v4 going from left to right);
second through vias penetrating the first semiconductor chip and spaced apart from each other in the first horizontal direction (Fig. 1B, where going forward the vias of the first chip (1c) will be considered 1c_v1, 1c_v2, 1c_v3, and 1c_v4 going from left to right);
third through vias penetrating the second semiconductor chip and spaced apart from each other in the first horizontal direction (Fig. 1B, where going forward the vias of the second chip (1b) will be considered 1b_v1, 1b_v2 going from left to right);
a connection structure comprising:
first connection pads between the base chip and the first semiconductor chip (Fig. 1B; unlabeled bonding pads on either the top surface of chip (1d) or the bottom surface of chip (1c)); and
second connection pads between the first semiconductor chip and the second semiconductor chip (Fig. 1B; unlabeled bonding pads on either the top surface of chip (1c) or the bottom surface of chip (1b));
wherein at least one of the first through vias is offset from at least one of the second through vias in the vertical direction (Fig. 1B; for example, 1d_v1 is offset from 1c_v2), and
wherein at least one of the second through vias is offset from at least one of the third through vias in the vertical direction (Fig. 1B; for example, 1c_v1 is offset from 1b_v2).
Tanie is silent with respect to a mold layer and underfill layers.
Egawa teaches a semiconductor package (Fig. 2) including a mold layer (25) at least partially covering the semiconductor chip stack (chips 2) on the top surface of the base chip (bottommost chip 2); and underfill material layers (24) between the mold layer and between the first semiconductor chip and the second semiconductor chip (para. 0060-0061).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the mold layer and the underfill layers as taught by Egawa within the device of Tanie to arrive at the claimed invention for the purpose of providing protection to the device of Tanie (Egawa para. 0060-0061).
Re claim 17, Tanie teaches wherein a first distance, in the first horizontal direction, between the first through vias is different from a second distance, in the first horizontal direction, between the second through vias (Fig. 1B; for example, the distance between 1d_v1 and 1d_v2 is different from the distance between 1c_v1 and 1c_v2).
Re claim 18, Tanie teaches wherein a third distance, in the first horizontal direction, between the second through vias is different from a fourth distance, in the first horizontal direction, between the third through vias (Fig. 1B; for example, the distance between 1c_v1 and 1c_v2 is different from the distance between 1b_v1 and 1b_v2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/Examiner, Art Unit 2899
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