DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 06/29/2026, in which claims 10, 17 were amended, claims 14, 19 were cancelled, claims 21-22 were added, has been entered.
Claim Objections
The status of claim 15 is not in accordance with 37 CFR 1.121(c) which requires claims having the status of "currently amended," or "withdrawn" if also being amended, shall include markings. In this case, claim 15 does not include any markings, thus the status of claim 15 should be “(Previously presented)” or “(Original)”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation “wherein the gate structure is thermally coupled to the metal structure by way of a diode”. The claim does not recite which structure of the diode result to “thermally coupled” of the gate structure and the metal structure. Therefore, the scope of the claim is unclear and indefinite.
“when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255, 85 USPQ2d 1654, 1663 (Fed. Cir. 2008)… without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim. Ariad Pharmaceuticals., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1353, 94 USPQ2d 1161, 1173 (Fed. Cir. 2010) (en banc)… See also Datamize LLC v. Plumtree Software Inc., 417 F.3d 1342, 75 USPQ2d 1801 (Fed. Cir. 2005) where a claim directed to a software based system for creating a customized computer interface screen recited that the screen be "aesthetically pleasing," which is an intended result and does not provide a clear cut indication of scope because it imposed no structural limits on the screen.” MPEP 2173.05 (g).
It appears from Applicant’s specification and from Applicant’s arguments that the particular diode structure of “The first doped region 310, the second doped region 312, and the depletion region 311 are formed of semiconductor materials, such as silicon or silicon germanium and have thermal conductivities are about two orders of magnitude greater than that of dielectric materials, such as silicon oxide” are essential and critical to achieve the claimed result of “the gate structure is thermally coupled to the metal structure by a diode”. However, those essential structures were not recited in the claim.
"Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment." Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004). See also Liebel-Flarsheim Co. v. Medrad Inc., 358 F.3d 898, 906, 69 USPQ2d 1801, 1807 (Fed. Cir. 2004). See MPEP 2111.01 II.
Therefore, claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: “The first doped region 310, the second doped region 312, and the depletion region 311 (of the diode) are formed of semiconductor materials, such as silicon or silicon germanium and have thermal conductivities are about two orders of magnitude greater than that of dielectric materials, such as silicon oxide.”
Claims 2-9 depending from the rejected claim 1 noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
For the purpose of this Action, if a gate structure is electrical coupled to the metal structure by way of a diode, the intended result of “the gate is thermally coupled to the metal structure by way of a diode” will be achieve. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 II.
Regarding claim 22, claim 22 recites “wherein the diode allows heat passage to the seal ring metal structure but prevents the seal ring metal structure from being electrically coupled to the gate structure.” However, no particular structure of the diode was recited in the claim to achieve the claimed intended result. Therefore, the scope of the claim is unclear and undefine. As best understood from Applicant’s arguments, thermal conductivity of diode can be achieved due to “the first doped region 310, the second doped region 312, and the depletion region 311 (of the diode) are formed of semiconductor materials, such as silicon or silicon germanium and have thermal conductivities are about two orders of magnitude greater than that of dielectric materials, such as silicon oxide.” However, these particular structures of the diode was omitted in the claim. Thus, claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01.
“when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255, 85 USPQ2d 1654, 1663 (Fed. Cir. 2008)… without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim. Ariad Pharmaceuticals., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1353, 94 USPQ2d 1161, 1173 (Fed. Cir. 2010) (en banc)… See also Datamize LLC v. Plumtree Software Inc., 417 F.3d 1342, 75 USPQ2d 1801 (Fed. Cir. 2005) where a claim directed to a software based system for creating a customized computer interface screen recited that the screen be "aesthetically pleasing," which is an intended result and does not provide a clear cut indication of scope because it imposed no structural limits on the screen.” MPEP 2173.05 (g).
For the purpose of this Action, any diode connected between the gate structure and the metal structure would capable of performing the claimed intended function of “wherein the diode allows heat passage to the seal ring metal structure but prevents the seal ring metal structure from being electrically coupled to the gate structure.”
Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 15 and 21 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 15 recites ‘the device structure of claim 14”, however claim 14 was cancelled. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 21 depending from the rejected claim 15 noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20160126324) in view of Lin et al. (US Pub. 20230361056).
Regarding claim 1, Yu et al. discloses in Fig. 1, Fig. 2, Fig. 4, Fig. 5 an integrated circuit (IC) chip, comprising:
a device region [12 and 11];
an interconnect structure [17] disposed over the device region [12 and 11]; and
a seal ring [13] surrounding the device region [12 and 11] and the interconnect structure [17], wherein the seal ring [13] comprises a metal structure [50].
wherein the device region [12 and 11] comprises a transistor [14] having a gate structure [14a].
Yu et al. fails to discloses
wherein the gate structure is thermally coupled to the metal structure by way of a diode.
Lin et al. discloses in Fig. 1, Fig. 3, paragraph [0026], [0030], [0031], [0036]
wherein the gate structure [41] is electrically and thermally coupled to the metal structure [12] by way of a diode [20][See 112b above].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin et al. into the method of Yu et al. to include wherein the gate structure is electrically and thermally coupled to the metal structure by way of a diode. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing superior physical and electrostatic discharge (ESD) protection for the device portion [paragraph [0031] of Yu et al.].
Regarding claim 2, Yu et al. discloses in Fig. 1, Fig. 2, Fig. 4, Fig. 5
wherein the transistor [14] is spaced apart from the seal ring [13] by a distance.
Yu et al. fails to disclose
the distance between about 100 µm and about 200 µm.
However, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Yu et al. to provide the distance between about 100 µm and about 200 µm. The ordinary artisan would have been motivated to modify Yu et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to provide optimal distance between the transistor and the seal ring for their intended operation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20160126324) in view of Lin et al. (US Pub. 20230361056) as applied to claim 1 above and further in view of Huang et al. (US Pub. 20210335690).
Regarding claim 3, Yu et al. and Lin et al. fails to disclose
wherein the transistor further comprises a plurality of channel members extending between a source feature and a drain feature, wherein the gate structure wraps around each of the plurality of channel members, wherein the gate structure is spaced apart from the source feature and the drain feature by a plurality of inner spacer features.
Huang et al. discloses in Fig. 20B, Fig. 31, paragraph [0013], [0043], [0046], [0058]
wherein the transistor further comprises a plurality of channel members [54 or 55] extending between a source feature and a drain feature [92], wherein the gate structure [100 and 102] wraps around each of the plurality of channel members [55], wherein the gate structure [100 and 102] is spaced apart from the source feature and the drain [92] feature by a plurality of inner spacer features [90].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang et al. into the method of Yu et al. and Lin et al. to include wherein the transistor further comprises a plurality of channel members extending between a source feature and a drain feature, wherein the gate structure wraps around each of the plurality of channel members, wherein the gate structure is spaced apart from the source feature and the drain feature by a plurality of inner spacer features. The ordinary artisan would have been motivated to modify Yu et al. and Lin et al. in the above manner for the purpose of suitable type of transistor, providing nano-FETs for enhanced performance and increased integration density [paragraph 0012] of Huang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20160126324) in view of Lin et al. (US Pub. 20230361056) as applied to claim 1 above and further in view of Senapati et al. (US Pub. 20250185377) and Okubo (US Pub. 20190081032)
Regarding claims 4-5, 7-8, Yu et al. and Lin et al. fails to disclose
wherein the diode comprises:
a well region;
a stack disposed over the well region and comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
a first doped region and a second doped region in the stack;
a first contact electrically coupled to the first doped region; and
a second contact electrically coupled to the second doped region;
wherein the well region comprises silicon and a p-type dopant;
wherein the first doped region comprises a first type dopant,
wherein the second doped region comprises a second type dopant different from the first type dopant;
wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant.
Senapati et al. discloses in Fig. 3, Fig. 15A,
wherein the diode [passive device] comprises:
a well region [212B] paragraph [0089]];
a stack [SiGe and Si] disposed over the well region [212B] and comprising a plurality of first semiconductor layers [Si] interleaved by a plurality of second semiconductor layers [SiGe];
a first doped region [one of N+ or P+] and a second doped region [another one of N+ or P+] in the stack [SiGe and Si][paragraph [0105]-[0106]];
a first contact electrically coupled to the first doped region [one of N+ or P+] [paragraph [0107]]; and
a second contact electrically coupled to the second doped region [another one of N+ or P+] [paragraph [0107]];
wherein the first doped region [one of N+ or P+] comprises a first type dopant,
wherein the second doped region [another one of N+ or P+] comprises a second type dopant different from the first type dopant;
wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant.
Okubo discloses in Fig. 34, paragraph [0197]-[0198], [0207], [0213], [0216], [0229].
wherein the diode comprises:
a well region [P well];
a stack [76] disposed over the well region [P well];
a first doped region [one of 82a or 84a] and a second doped region [another one of 84a] in the stack [76];
a first contact [92a] electrically coupled to the first doped region [one of 82a or 84a]; and
a second contact [92a] electrically coupled to the second doped region [another one of 82a or 84a];
wherein the well region [P well] comprises silicon and a p-type dopant;
wherein the first doped region [one of 82a or 84a] comprises a first type dopant,
wherein the second doped region [another one of 82a or 84a] comprises a second type dopant different from the first type dopant;
wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okubo and Senapati et al. into the method of Yu et al. and Lin et al. to include wherein the diode comprises: a well region; a stack disposed over the well region and comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers; a first doped region and a second doped region in the stack; a first contact electrically coupled to the first doped region; and a second contact electrically coupled to the second doped region; wherein the well region comprises silicon and a p-type dopant; wherein the first doped region comprises a first type dopant, wherein the second doped region comprises a second type dopant different from the first type dopant; wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant. The ordinary artisan would have been motivated to modify Yu et al. and Lin et al. in the above manner for the purpose of providing suitable configuration of a diode that can be co-integrated with nanosheet FETs [paragraph [0056]-[0057] of Senapati et al.; paragraph [0195] of Okubo].
Regarding claim 6, Lin et al. discloses in Fig. 1, Fig. 3 the gate structure [41] is electrically coupled to a first node region [231] of the diode and the metal structure [12, 10] is electrically coupled to a second node region [202] of the diode.
Okubo and Senapati et al. discloses a first node region and a second node region of the diode comprises the first doped region and the second doped region, respectively.
Thus, the combination of Yu et al., Lin et al., Okubo and Senapati et al. would result to “the gate structure is electrically coupled to the first doped region and the metal structure is electrically coupled to the second doped region.”
Claims 10, 12-13, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Senapati et al. (US Pub. 20250185377) in view of Yu et al. (US Pub. 20160126324), Lin et al. (US Pub. 20230361056) and Zhou et al. (US Pub. 2240429226).
Regarding claim 10, Senapati et al. discloses in Fig. 2A, Fig. 15A a device structure, comprising:
a backside dielectric layer [etch stop layer][paragraph [0091]];
a transistor comprising:
a first well region [212B in logic region] disposed on the backside dielectric layer [etch stop layer],
a plurality of nanostructures disposed one over another over the first well region [Si region 212B], and
a gate structure wrapping around each of the plurality of nanostructures [paragraph [0089], [0103]];
a diode comprising:
a second well region [212B in passive region] disposed on the backside dielectric layer [etch stop layer],
a stack over the second well region [212B in passive region] and comprising a plurality of silicon layers interleaved by a plurality of silicon germanium layers,
a first doped region [one of N+ or P+] and a second doped region [another one of N+ or P+] in the stack and spaced apart by a depletion region, and
a floating gate structure over the depletion region;
a gate contact via disposed on the gate structure, a first contact disposed on the first doped region,
Senapati et al. fails to disclose
a seal ring metal structure spaced apart from the transistor by a spacing,
wherein the gate structure is electrically coupled to the first doped region,
wherein the gate structure is electrically coupled to the first doped region by way of the gate contact via disposed on the gate structure, the first contact disposed on the first doped region, a first contact via disposed on the first contact, and a first metal line disposed on the gate contact via and the first contact via.
wherein the second doped region is electrically coupled to the seal ring metal structure.
Yu et al. discloses in Fig. 1, Fig. 4, Fig. 5, paragraph [0017], [0023], [0028]-[0029]
a seal ring metal structure [50] spaced apart from a transistor [14] by a spacing,
Lin et al. discloses in Fig. 1, Fig. 3, paragraph [0026], [0030], [0031], [0036]
wherein the gate structure [41] of a transistor is electrically coupled to a first node region of a diode, wherein a second node region of the diode is electrically coupled to the seal ring metal structure [12, 10, 11].
Senapati et al. discloses a first node region and a second node region of the diode comprises the first doped region and the second doped region, respectively.
Zhou et al. discloses in Fig. 2
wherein a gate structure is electrically coupled to a first doped region [206] by way of the gate contact via disposed on the gate structure [PC], the first contact disposed on the first doped region [206], a first contact via disposed on the first contact, and a first metal line [M1] disposed on the gate contact via and the first contact via.
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Thus, incorporating the teachings of Zhou et al., Yu et al. and Lin et al. into the method of Senapati et al. would result to “a seal ring metal structure spaced apart from the transistor by a spacing, the gate structure is electrically coupled to the first doped region, wherein the gate structure is electrically coupled to the first doped region by way of the gate contact via disposed on the gate structure, the first contact disposed on the first doped region, a first contact via disposed on the first contact, and a first metal line disposed on the gate contact via and the first contact via, wherein the second doped region is electrically coupled to the seal ring metal structure.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Lin et al. into the method of Senapati et al. to include a seal ring metal structure spaced apart from the transistor by a spacing, wherein the gate structure is electrically coupled to the first doped region, wherein the gate structure is electrically coupled to the first doped region by way of the gate contact via disposed on the gate structure, the first contact disposed on the first doped region, a first contact via disposed on the first contact, and a first metal line disposed on the gate contact via and the first contact via, wherein the second doped region is electrically coupled to the seal ring metal structure. The ordinary artisan would have been motivated to modify Senapati et al. in the above manner for the purpose of providing a sealing region that physically protects the transistor, allows to conduct electric currents and provides ESD protection to the transistor; providing suitable method for electrically coupling the gate structure to the first doped region to protect the gate oxide of the stacked FET [paragraph [0031] of Lin et al., paragraph [0029] of Yu et al., paragraph [0061]-[0062], [0064] of Zhou et al.].
Regarding claim 12, Senapati et al. discloses in Fig. 15A wherein the first doped region [N+] comprises an n-type dopant, wherein the second doped region [P+] comprises a p-type dopant.
Regarding claim 13, Senapati et al., Lin et al., Zhou et al. and Yu et al. fails to disclose
wherein the spacing is between about 100 µm and about 200 µm.
However, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Senapati et al., Zhou et al., Lin et al. and Yu et al. to provide wherein the spacing is between about 100 µm and about 200 µm. The ordinary artisan would have been motivated to modify Senapati et al., Zhou et al., Lin et al. and Yu et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to provide optimal distance between the transistor and the seal ring for their intended operation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 16, Senapati et al. discloses in Fig. 15A the floating gate structure is electrically floating.
Notes, “electrically floating” directs to manner of operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Senapati et al. (US Pub. 20250185377) in view of Yu et al. (US Pub. 20160126324), Lin et al. (US Pub. 20230361056) and Zhou et al. (US Pub. 2240429226) as applied to claim 10 above and further in view of Okubo (US Pub. 20190081032).
Regarding claim 11, Senapati et al. fails to disclose
wherein the first well region and the second well region comprise a p-type dopant.
Okubo discloses in Fig. 34A
wherein the first well region [P well of NMOS] and the second well region [P well of diode] comprise a p-type dopant.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okubo into the method of Senapati et al. to include wherein the first well region and the second well region comprise a p-type dopant. The ordinary artisan would have been motivated to modify Senapati et al. in the above manner for the purpose of providing suitable dopant of first and second well region.
Claims 17-18, 20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Senapati et al. (US Pub. 20250185377) in view of Yu et al. (US Pub. 20160126324) and Lin et al. (US Pub. 20230361056).
Regarding claim 17, Senapati et al. discloses in Fig. 2A, Fig. 15A a device structure, comprising:
a transistor comprising:
a plurality of nanostructures, and
a gate structure wrapping around each of the plurality of nanostructures [paragraph [0089], [0103]];
a diode comprising:
a stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers,
a first doped region [N+] and a second doped region [P+] in the stack;
wherein the first doped region [N+] comprises an n-type dopant, wherein the second doped region [P+] comprises a p-type dopant.
Senapati et al. fails to disclose
a seal ring metal structure spaced apart from the transistor by a spacing,
wherein the gate structure is electrically coupled to the first doped region,
wherein the second doped region is electrically coupled to the seal ring metal structure.
Yu et al. discloses in Fig. 1, Fig. 4, Fig. 5, paragraph [0017], [0023], [0028]-[0029]
a seal ring metal structure [50] spaced apart from a transistor [14] by a spacing,
Lin et al. discloses in Fig. 1, Fig. 3, paragraph [0026], [0030], [0031], [0036]
wherein the gate structure [41] of a transistor is electrically coupled to a first node region of a diode, wherein a second node region of the diode is electrically coupled to the seal ring metal structure [12, 10, 11].
Senapati et al. discloses a first node region and a second node region of the diode comprises the first doped region and the second doped region, respectively.
Thus, incorporating the teachings of Yu et al. and Lin et al. into the method of Senapati et al. would result to “a seal ring metal structure spaced apart from the transistor by a spacing, the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Lin et al. into the method of Senapati et al. to include a seal ring metal structure spaced apart from the transistor by a spacing, wherein the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure. The ordinary artisan would have been motivated to modify Senapati et al. in the above manner for the purpose of providing a sealing region that physically protects the transistor, allows to conduct electric currents and provides ESD protection to the transistor [paragraph [0031] of Lin et al., paragraph [0029] of Yu et al.].
Regarding claim 18, Senapati et al. discloses in Fig. 14A, 15A
wherein the plurality of nanostructures comprise silicon,
wherein the plurality of first semiconductor layers comprise silicon,
wherein the plurality of second semiconductor layers comprise silicon germanium.
Regarding claim 20, Senapati et al., Lin et al. and Yu et al. fails to disclose
wherein the spacing is between about 100 µm and about 200 µm.
However, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Senapati et al., Lin et al. and Yu et al. to provide wherein the spacing is between about 100 µm and about 200 µm. The ordinary artisan would have been motivated to modify Senapati et al., Lin et al. and Yu et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to provide optimal distance between the transistor and the seal ring for their intended operation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 22, the combination of Senapati et al., Lin et al. and Yu et al. discloses every structure of the claim in a same arrangement as the claim including a diode connected between the gate structure and the metal structure. Thus, as stated in 112b above, the diode disclosed by combination of Senapati et al., Lin et al. and Yu et al. would capable of performing the claimed intended function of “wherein the diode allows heat passage to the seal ring metal structure but prevents the seal ring metal structure from being electrically coupled to the gate structure.”
"[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114 II.
Allowable Subject Matter
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 9, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “a second metal line disposed over the second contact via; a connection via disposed over the second metal line; and a third metal line disposed over the connection via, wherein the third metal line is physically coupled to the metal structure of the seal ring” of claim 9 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Response to Arguments
Applicant’s arguments with respect to claims 10-13, 15-18, 20-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 06/9/2026 have been fully considered but they are not persuasive.
As stated above, Applicant’s arguments that the particular diode structure of “The first doped region 310, the second doped region 312, and the depletion region 311 are formed of semiconductor materials, such as silicon or silicon germanium and have thermal conductivities are about two orders of magnitude greater than that of dielectric materials, such as silicon oxide” is essential to achieve the claimed result of “the gate structure is thermally coupled to the metal structure by a diode”. However, those essential structures were not recited in the claim. Therefore, claims 1-9 are still rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements.
Regarding Applicant’s arguments on page 11, Examiner respectfully disagreed because Lin et al. does not disclose diode 20 is a P/N Junction Diode. Lin et al. does not disclose anode 201 is P doped and cathode 202 is N doped. paragraph [0040] of Bertin (US Pub. 20180034447) and paragraph [0048] of Bhattachryya (US Pub. 20050001232) provided evidences that a diode can have N doped anode and P doped cathode. Therefore, Applicant’s arguments that anode 201 must be an P doped region and cathode 202 must be an N doped region are not persuasive.
Further, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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