DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation “wherein the gate structure is thermally coupled to the metal structure by way of a diode”. It is unclear the meaning of “thermally coupled.”
Fig. 3 and claim 4 appear to disclose the gate structure is electrically coupled to the metal structure by the diode.
Thus, for the purpose of this Action, the above limitation of claim 1 will be interpreted and examined as -- wherein the gate structure is electrically coupled to the metal structure by way of a diode --
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20160126324) in view of Lin et al. (US Pub. 20230361056).
Regarding claim 1, Yu et al. discloses in Fig. 1, Fig. 2, Fig. 4, Fig. 5 an integrated circuit (IC) chip, comprising:
a device region [12 and 11];
an interconnect structure [17] disposed over the device region [12 and 11]; and
a seal ring [13] surrounding the device region [12 and 11] and the interconnect structure [17], wherein the seal ring [13] comprises a metal structure [50].
wherein the device region [12 and 11] comprises a transistor [14] having a gate structure [14a].
Yu et al. fails to discloses
wherein the gate structure is electrically coupled to the metal structure by way of the diode.
Lin et al. discloses in Fig. 1, Fig. 3, paragraph [0026], [0030], [0031], [0036]
wherein the gate structure [41] is electrically coupled to the metal structure [12, 10, 11] by way of a diode [20].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin et al. into the method of Yu et al. to include wherein the gate structure is electrically coupled to the metal structure by way of a diode. The ordinary artisan would have been motivated to modify Yu et al. in the above manner for the purpose of providing superior physical and electrostatic discharge (ESD) protection for the device portion [paragraph [0031] of Yu et al.].
Regarding claim 2, Yu et al. discloses in Fig. 1, Fig. 2, Fig. 4, Fig. 5
wherein the transistor [14] is spaced apart from the seal ring [13] by a distance.
Yu et al. fails to disclose
the distance between about 100 µm and about 200 µm.
However, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Yu et al. to provide the distance between about 100 µm and about 200 µm. The ordinary artisan would have been motivated to modify Yu et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to provide optimal distance between the transistor and the seal ring for their intended operation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20160126324) in view of Lin et al. (US Pub. 20230361056) as applied to claim 1 above and further in view of Huang et al. (US Pub. 20210335690).
Regarding claim 3, Yu et al. and Lin et al. fails to disclose
wherein the transistor further comprises a plurality of channel members extending between a source feature and a drain feature, wherein the gate structure wraps around each of the plurality of channel members, wherein the gate structure is spaced apart from the source feature and the drain feature by a plurality of inner spacer features.
Huang et al. discloses in Fig. 20B, Fig. 31, paragraph [0013], [0043], [0046], [0058]
wherein the transistor further comprises a plurality of channel members [54 or 55] extending between a source feature and a drain feature [92], wherein the gate structure [100 and 102] wraps around each of the plurality of channel members [55], wherein the gate structure [100 and 102] is spaced apart from the source feature and the drain [92] feature by a plurality of inner spacer features [90].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang et al. into the method of Yu et al. and Lin et al. to include wherein the transistor further comprises a plurality of channel members extending between a source feature and a drain feature, wherein the gate structure wraps around each of the plurality of channel members, wherein the gate structure is spaced apart from the source feature and the drain feature by a plurality of inner spacer features. The ordinary artisan would have been motivated to modify Yu et al. and Lin et al. in the above manner for the purpose of suitable type of transistor, providing nano-FETs for enhanced performance and increased integration density [paragraph 0012] of Huang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 20160126324) in view of Lin et al. (US Pub. 20230361056) as applied to claim 1 above and further in view of Senapati et al. (US Pub. 20250185377) and Okubo (US Pub. 20190081032)
Regarding claims 4-5, 7-8, Yu et al. and Lin et al. fails to disclose
wherein the diode comprises:
a well region;
a stack disposed over the well region and comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
a first doped region and a second doped region in the stack;
a first contact electrically coupled to the first doped region; and
a second contact electrically coupled to the second doped region;
wherein the well region comprises silicon and a p-type dopant;
wherein the first doped region comprises a first type dopant,
wherein the second doped region comprises a second type dopant different from the first type dopant;
wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant.
Senapati et al. discloses in Fig. 3, Fig. 15A,
wherein the diode [passive device] comprises:
a well region [212B] paragraph [0089]];
a stack [SiGe and Si] disposed over the well region [212B] and comprising a plurality of first semiconductor layers [Si] interleaved by a plurality of second semiconductor layers [SiGe];
a first doped region [one of N+ or P+] and a second doped region [another one of N+ or P+] in the stack [SiGe and Si][paragraph [0105]-[0106]];
a first contact electrically coupled to the first doped region [one of N+ or P+] [paragraph [0107]]; and
a second contact electrically coupled to the second doped region [another one of N+ or P+] [paragraph [0107]];
wherein the first doped region [one of N+ or P+] comprises a first type dopant,
wherein the second doped region [another one of N+ or P+] comprises a second type dopant different from the first type dopant;
wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant.
Okubo discloses in Fig. 34, paragraph [0197]-[0198], [0207], [0213], [0216], [0229].
wherein the diode comprises:
a well region [P well];
a stack [76] disposed over the well region [P well];
a first doped region [one of 82a or 84a] and a second doped region [another one of 84a] in the stack [76];
a first contact [92a] electrically coupled to the first doped region [one of 82a or 84a]; and
a second contact [92a] electrically coupled to the second doped region [another one of 82a or 84a];
wherein the well region [P well] comprises silicon and a p-type dopant;
wherein the first doped region [one of 82a or 84a] comprises a first type dopant,
wherein the second doped region [another one of 82a or 84a] comprises a second type dopant different from the first type dopant;
wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okubo and Senapati et al. into the method of Yu et al. and Lin et al. to include wherein the diode comprises: a well region; a stack disposed over the well region and comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers; a first doped region and a second doped region in the stack; a first contact electrically coupled to the first doped region; and a second contact electrically coupled to the second doped region; wherein the well region comprises silicon and a p-type dopant; wherein the first doped region comprises a first type dopant, wherein the second doped region comprises a second type dopant different from the first type dopant; wherein the first type dopant is an n-type dopant, wherein the second type dopant is a p-type dopant. The ordinary artisan would have been motivated to modify Yu et al. and Lin et al. in the above manner for the purpose of providing suitable configuration of a diode that can be co-integrated with nanosheet FETs [paragraph [0056]-[0057] of Senapati et al.; paragraph [0195] of Okubo].
Regarding claim 6, Lin et al. discloses in Fig. 1, Fig. 3 the gate structure [41] is electrically coupled to a first node region [231] of the diode and the metal structure [12, 10] is electrically coupled to a second node region [202] of the diode.
Okubo and Senapati et al. discloses a first node region and a second node region of the diode comprises the first doped region and the second doped region, respectively.
Thus, the combination of Yu et al., Lin et al., Okubo and Senapati et al. would result to “the gate structure is electrically coupled to the first doped region and the metal structure is electrically coupled to the second doped region.”
Claims 10, 12-13, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Senapati et al. (US Pub. 20250185377) in view of Yu et al. (US Pub. 20160126324) and Lin et al. (US Pub. 20230361056).
Regarding claim 10, Senapati et al. discloses in Fig. 2A, Fig. 15A a device structure, comprising:
a backside dielectric layer [etch stop layer][paragraph [0091]];
a transistor comprising:
a first well region [212B in logic region] disposed on the backside dielectric layer [etch stop layer],
a plurality of nanostructures disposed one over another over the first well region [Si region 212B], and
a gate structure wrapping around each of the plurality of nanostructures [paragraph [0089], [0103]];
a diode comprising:
a second well region [212B in passive region] disposed on the backside dielectric layer [etch stop layer],
a stack over the second well region [212B in passive region] and comprising a plurality of silicon layers interleaved by a plurality of silicon germanium layers,
a first doped region [one of N+ or P+] and a second doped region [another one of N+ or P+] in the stack and spaced apart by a depletion region, and
a floating gate structure over the depletion region.
Senapati et al. fails to disclose
a seal ring metal structure spaced apart from the transistor by a spacing,
wherein the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure.
Yu et al. discloses in Fig. 1, Fig. 4, Fig. 5, paragraph [0017], [0023], [0028]-[0029]
a seal ring metal structure [50] spaced apart from a transistor [14] by a spacing,
Lin et al. discloses in Fig. 1, Fig. 3, paragraph [0026], [0030], [0031], [0036]
wherein the gate structure [41] of a transistor is electrically coupled to a first node region of a diode, wherein a second node region of the diode is electrically coupled to the seal ring metal structure [12, 10, 11].
Senapati et al. discloses a first node region and a second node region of the diode comprises the first doped region and the second doped region, respectively.
Thus, incorporating the teachings of Yu et al. and Lin et al. into the method of Senapati et al. would result to “a seal ring metal structure spaced apart from the transistor by a spacing, the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Lin et al. into the method of Senapati et al. to include a seal ring metal structure spaced apart from the transistor by a spacing, wherein the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure. The ordinary artisan would have been motivated to modify Senapati et al. in the above manner for the purpose of providing a sealing region that physically protects the transistor, allows to conduct electric currents and provides ESD protection to the transistor [paragraph [0031] of Lin et al., paragraph [0029] of Yu et al.].
Regarding claim 12, Senapati et al. discloses in Fig. 15A wherein the first doped region [N+] comprises an n-type dopant, wherein the second doped region [P+] comprises a p-type dopant.
Regarding claims 13 and 20, Senapati et al., Lin et al. and Yu et al. fails to disclose
wherein the spacing is between about 100 µm and about 200 µm.
However, Applicant has not provided any criticality of the claimed range. It would have been obvious to modify Senapati et al., Lin et al. and Yu et al. to provide wherein the spacing is between about 100 µm and about 200 µm. The ordinary artisan would have been motivated to modify Senapati et al., Lin et al. and Yu et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to provide optimal distance between the transistor and the seal ring for their intended operation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 16, Senapati et al. discloses in Fig. 15A the floating gate structure is electrically floating.
Notes, “electrically floating” directs to manner of operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claim 17, Senapati et al. discloses in Fig. 2A, Fig. 15A a device structure, comprising:
a transistor comprising:
a plurality of nanostructures, and
a gate structure wrapping around each of the plurality of nanostructures [paragraph [0089], [0103]];
a diode comprising:
a stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers,
a first doped region [one of N+ or P+] and a second doped region [another one of N+ or P+] in the stack;
Senapati et al. fails to disclose
a seal ring metal structure spaced apart from the transistor by a spacing,
wherein the gate structure is electrically coupled to the first doped region,
wherein the second doped region is electrically coupled to the seal ring metal structure.
Yu et al. discloses in Fig. 1, Fig. 4, Fig. 5, paragraph [0017], [0023], [0028]-[0029]
a seal ring metal structure [50] spaced apart from a transistor [14] by a spacing,
Lin et al. discloses in Fig. 1, Fig. 3, paragraph [0026], [0030], [0031], [0036]
wherein the gate structure [41] of a transistor is electrically coupled to a first node region of a diode, wherein a second node region of the diode is electrically coupled to the seal ring metal structure [12, 10, 11].
Senapati et al. discloses a first node region and a second node region of the diode comprises the first doped region and the second doped region, respectively.
Thus, incorporating the teachings of Yu et al. and Lin et al. into the method of Senapati et al. would result to “a seal ring metal structure spaced apart from the transistor by a spacing, the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yu et al. and Lin et al. into the method of Senapati et al. to include a seal ring metal structure spaced apart from the transistor by a spacing, wherein the gate structure is electrically coupled to the first doped region, wherein the second doped region is electrically coupled to the seal ring metal structure. The ordinary artisan would have been motivated to modify Senapati et al. in the above manner for the purpose of providing a sealing region that physically protects the transistor, allows to conduct electric currents and provides ESD protection to the transistor [paragraph [0031] of Lin et al., paragraph [0029] of Yu et al.].
Regarding claims 18-19, Senapati et al. discloses in Fig. 14A, 15A
wherein the plurality of nanostructures comprise silicon,
wherein the plurality of first semiconductor layers comprise silicon,
wherein the plurality of second semiconductor layers comprise silicon germanium.
wherein the first doped region [N+] comprises an n-type dopant, wherein the second doped region [P+] comprises a p-type dopant.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Senapati et al. (US Pub. 20250185377) in view of Yu et al. (US Pub. 20160126324) and Lin et al. (US Pub. 20230361056) as applied to claim 10 above and further in view of Okubo (US Pub. 20190081032).
Regarding claim 11, Senapati et al. fails to disclose
wherein the first well region and the second well region comprise a p-type dopant.
Okubo discloses in Fig. 34A
wherein the first well region [P well of NMOS] and the second well region [P well of diode] comprise a p-type dopant.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okubo into the method of Senapati et al. to include wherein the first well region and the second well region comprise a p-type dopant. The ordinary artisan would have been motivated to modify Senapati et al. in the above manner for the purpose of providing suitable dopant of first and second well region.
Allowable Subject Matter
Claims 9, 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “a first contact via disposed on the first contact; a second contact via disposed on the second contact; a first metal line disposed over the gate contact via and the first contact via; a second metal line disposed over the second contact via; a connection via disposed over the second metal line; and a third metal line disposed over the connection via, wherein the third metal line is physically coupled to the metal structure of the seal ring” of claim 9 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Regarding claim 14, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “a first contact via disposed on the first contact, and a first metal line disposed on the gate contact via and the first contact via” of claim 14 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Claim 15 is allowable based on their dependence on claim 14, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
Prosecution Insights