CTNF 18/531,235 CTNF 89644 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is responsive to the following communications: the Amendment filed 5/13/2026. Claims 1-20 are pending. Information Disclosure Statement The information disclosure statements (IDS) submitted on 12/6/2023 and 11/11/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Election/Restrictions 08-25 AIA Applicant's election with traverse of Species II in the reply filed on 5/13/2026 is acknowledged. The traversal is on the ground(s) that the Office has not shown that Species I and Species II are mutually exclusive (Remarks 9) . This is not found persuasive because Species I is directed to the configuration disclosed in paragraph [0055] of the Specification of the current application, specifically as stated wherein “the lower end of the vertical power structure 120 may be disposed on a level higher than a level of the interfacial surface between the substrate 101 and the device isolation layer 110” and Species II is directed to the configuration shown in Figure 2, wherein the lower end of the vertical power structure 120 is disposed on a level lower than a level of the interfacial surface between the substrate 101 and the device isolation layer 110. These two configurations are mutually exclusive from one another, because they cannot coexist at the same time. For example, it is not possible for the lower end of the vertical power structure to be a level which is both lower and higher than a level of the interfacial surface between the substrate and the device isolation layer . The requirement is still deemed proper and is therefore made FINAL. 08-05 AIA Claim s 7 and 9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/13/2026 . Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 6, 10-11 and 13 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. (US 2021/0028112 A1, hereinafter “Kim”) . Regarding independent claim 1 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose a semiconductor device, comprising: a substrate 101 (“substrate”- ¶0025) including an active region 102 (“active region”- ¶0025) extending in a first direction; a gate structure GS (“gate structure”- ¶0028) on the active region 102, the gate structure GS extending in a second direction, the second direction intersecting the first direction, and the gate structure GS intersecting the active region 102; a source/drain region 110 (“source/drain region”- ¶0027) on the active region 102, the source/drain region 110 on at least one side of the gate structure GS; a contact structure V1 (“metal vias”- ¶0046) on the source/drain region 110 and connected to the source/drain region 110 (¶¶0044, 0046); a device isolation layer 162 (“device isolation layer”- ¶0029) surrounding the active region 102 on the substrate 101; an interlayer insulating layer 165/171 (collectively 165 “interlayer insulation layer” and 171 “etch stop layer”- ¶¶0040, 0047) on the device isolation layer 162, the interlayer insulating layer 165/171 covering the gate structure GS and the source/drain region 110; a vertical power structure 180 (“contact structure”- ¶0040) penetrating through the device isolation layer 162 and the interlayer insulating layer 165/171, the vertical power structure 180 being connected to the contact structure V1 and being below the contact structure V1; a rear power structure 120 (“conductive wiring”- ¶0033, specifically the configuration shown in Figure 5) surrounding an entirety of a lower surface of the vertical power structure 180 and a portion of a side surface of the vertical power structure 180, the rear power structure 120 being electrically connected to the vertical power structure 180 (¶0044); a vertical insulating film 130 (“insulation capping layer”- ¶0040, which extends in the vertical direction) covering the side surface of the vertical power structure 120, the vertical insulating film 130 being between the vertical power structure 180 and the rear power structure 120; and a rear insulating film 251 (“dielectric liner”- ¶0055) covering a side surface of the rear power structure 120. Regarding claim 6 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose wherein a level of an upper end of the rear power structure 120 is higher than a level of an interfacial surface (i.e., the bottommost interface between 162 and 102) between the device isolation layer 162 and the substrate 101. Regarding claim 10 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose wherein the vertical power structure 180 includes at least one of tungsten (W), molybdenum (Mo), copper (Cu) and cobalt (Co) (¶0056). Regarding claim 11 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose wherein the rear power structure 120 includes a same material as a material of the vertical power structure 180 (¶0056). Regarding claim 13 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose wherein a portion of the contact structure V1 overlaps a portion of the source/drain region 110 in the first direction . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-5, 8, 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 2 (which claims 3-5 depend from) , the prior art of record including Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein an upper end of the vertical power structure includes a recess, and a portion of the contact structure extends into the recess of the vertical power structure”. Regarding claim 8 , the prior art of record including Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a lower end of the vertical insulating film is lower than a level of an interfacial surface between the substrate and the device isolation layer”. Regarding claim 12 , the prior art of record including Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a lower end of the vertical power structure and a lower end of the vertical insulating film are lower than a level of an interfacial surface of the device isolation layer and the substrate”. Regarding claim 14 , the prior art of record including Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] semiconductor device… further comprising: a plurality of channel layers on the active region and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction, and the plurality of channel layers are surrounded by the gate structure”. 12-151-07 AIA 07-97 12-51-07 Claim s 15-20 are allowed. Regarding independent claim 15 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose a semiconductor device, comprising: a substrate 101 (“substrate”- ¶0025) including an active region 102 (“active region”- ¶0025) extending in a first direction; a gate structure GS (“gate structure”- ¶0028) on the active region 102, the gate structure GS extending in a second direction, the second direction intersecting the first direction, and the gate structure GS intersecting the active region 102; a source/drain region 110 (“source/drain region”- ¶0027) on the active region 102, the source/drain region 110 on at least one side of the gate structure 102; a contact structure V1 (“metal vias”- ¶0046) on the source/drain region 110 and connected to the source/drain region 110 (¶¶0044, 0046); a device isolation layer 162 (“device isolation layer”- ¶0029) surrounding the active region 102 on the substrate 101; an interlayer insulating layer 165/171 (collectively 165 “interlayer insulation layer” and 171 “etch stop layer”- ¶¶0040, 0047) on the device isolation layer 162, the interlayer insulating layer 165/171 covering the gate structure GS and the source/drain region 110; a vertical power structure 185 (“conductive material”- ¶0055) extending in a third direction, the third direction being perpendicular to an upper surface of the substrate 101, and the vertical power structure 180 being connected to the contact structure V1 (¶¶0044, 0046); a first conductive barrier 182 (“conductive barrier”- ¶0055) on a side surface of the vertical power structure; a rear power structure 120 (“conductive wiring”- ¶0033, specifically the configuration shown in Figure 5) electrically connected to the vertical power structure 185, the rear power structure 120 penetrating through a portion of the substrate 101 and a portion of the device isolation layer 162; and a rear insulating film 251 (“dielectric liner”- ¶0055) covering a side surface of the rear power structure 120, wherein the rear power structure 120 overlaps the vertical power structure 185 in the second direction and the third direction, a level of an upper end of the rear power structure 120 is higher than a level of a lower end of the vertical power structure 185, and a width of an upper end of the rear power structure 120 is greater than a width of the lower end of the vertical power structure 185. Kim does not expressly disclose wherein the vertical power structure penetrates through the substrate. Thus, regarding independent claim 15 , the claim is allowed , because the prior art of record including Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a vertical power structure penetrating through the substrate”. Claims 16-19 are allowed as being dependent on allowed claim 15. Regarding independent claim 20 , Figures 1-2 and 5 of Kim, specifically the overall configuration shown in Figure 1-2 implemented with the embodiment of 120 shown in Figure 5) disclose a semiconductor device, comprising: a substrate 101 (“substrate”- ¶0025) including an active region 102 (“active region”- ¶0025) extending in a first direction; a gate structure GS (“gate structure”- ¶0028) on the active region 102, the gate structure GS extending in a second direction, the second direction intersecting the first direction; a source/drain region 110 (“source/drain region”- ¶0027) on the active region 102, the source/drain region 110 on at least one side of the gate structure GS; a contact structure V1 (“metal vias”- ¶0046) on the source/drain region 110 and connected to the source/drain region 110 (¶¶0044, 0046); a device isolation layer 162 (“device isolation layer”- ¶0029) surrounding the active region 102 on the substrate 101; an interlayer insulating layer 165/171 (collectively 165 “interlayer insulation layer” and 171 “etch stop layer”- ¶¶0040, 0047) on the device isolation layer 162, the interlayer insulating layer 165/171 covering the gate structure GS and the source/drain region 110; a vertical power structure 185 (“conductive material”- ¶0055) penetrating through the device isolation layer 162 and the interlayer insulating layer 165/171, the vertical power structure 185 being connected to the contact structure V1 and being below the contact structure V1; a rear power structure 120 (“conductive wiring”- ¶0033, specifically the configuration shown in Figure 5) surrounding an entirety of a lower surface of the vertical power structure 185 and a portion of a side surface of the vertical power structure 185, the rear power structure 120 being electrically connected to the vertical power structure 185 (¶0044); a first conductive barrier 182 (“conductive barrier”- ¶0055) on a side surface of the vertical power structure 185 and the lower surface of the vertical power structure 185; a vertical insulating film 130 (“insulation capping layer”- ¶0040, which extends in the vertical direction) surrounding a side surface of the first conductive barrier 182. Kim does not expressly disclose a second conductive barrier on a side surface of the rear power structure and an upper surface of the rear power structure, a rear insulating film on a side surface of the second conductive barrier, wherein the vertical power structure extends into a recessed portion of the substrate, an upper end of the vertical power structure includes a recess, and a portion of the contact structure extends into the recess of the upper end of the vertical power structure. Thus, regarding independent claim 20 , the claim is allowed , because the prior art of record including Kim, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a second conductive barrier on a side surface of the rear power structure and an upper surface of the rear power structure”, “a rear insulating film on a side surface of the second conductive barrier, wherein the vertical power structure extends into a recessed portion of the substrate”, “an upper end of the vertical power structure includes a recess” and “a portion of the contact structure extends into the recess of the upper end of the vertical power structure”. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Xie et al. (US 2023/0130305 A1) , which discloses a semiconductor device comprising a vertical power structure penetrating multiple layers. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817 Application/Control Number: 18/531,235 Page 2 Art Unit: 2817 Application/Control Number: 18/531,235 Page 3 Art Unit: 2817 Application/Control Number: 18/531,235 Page 4 Art Unit: 2817 Application/Control Number: 18/531,235 Page 5 Art Unit: 2817 Application/Control Number: 18/531,235 Page 6 Art Unit: 2817 Application/Control Number: 18/531,235 Page 7 Art Unit: 2817 Application/Control Number: 18/531,235 Page 8 Art Unit: 2817 Application/Control Number: 18/531,235 Page 9 Art Unit: 2817 Application/Control Number: 18/531,235 Page 10 Art Unit: 2817 Application/Control Number: 18/531,235 Page 11 Art Unit: 2817 Application/Control Number: 18/531,235 Page 12 Art Unit: 2817
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