DETAILED ACTION
This Office Action is in response to Applicant’s application 18/531,423 filed on December 6, 2023 in which claims 1 to 19 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on December 6, 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on December 30, 2024, March 25, 2024 and July 18, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2018/0342475 (Wirz), U.S. 2021/0183773 (Rubin) and US. 2025/0105212 (Huang).
Regarding claim 1 Wirz teaches and suggests at annotated Figure 2A an integrated circuit (IC) package, comprising:
a die comprising, 126 [0022], a plurality of die interconnects. 110 [0019]; and
a substrate, 126 [0021], comprising a lower metallization layer, 130/112 [0021-22], extending in a first direction, e.g. Z direction as annotated, the lower metallization layer comprising a plurality of metal interconnects, 130/112 [0021-
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24], the plurality of metal interconnects comprising:
a first pad, 130 [0021], having a first surface, as annotated, and a second surface, as annotated, opposite the first surface, as shown, in a second direction orthogonal to the first direction, i.e. xy direction as annotated, the first pad having a first cross-sectional area extending in the first direction; and
a second pad, 112 [0024], coupled to the first surface, as shown, the second pad having a second cross-sectional area extending in the first direction, z direction, and suggests it is less than the first cross-sectional area; and
a solder joint, 114/253 [0024-25], coupled to the second pad, as shown, and a first die interconnect, e.g. 110, of the plurality of die interconnects, as shown, the first die interconnect having a third cross-sectional area extending in the first direction, as shown and Wirz suggests it is less than the first cross-sectional area, and the second cross-sectional area is at least equal to the third cross-sectional area.
Wirz does not explicitly teach a second cross-sectional area extending in the first direction less than the first cross-sectional area; and the second cross-sectional area is at least equal to the third cross-sectional area, i.e. Wirz does not teach the shapes of the pads and die interconnect structure in the xy plane
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Rubin is directed to semiconductor packaging. Rubin teaches at annotated Figure 1B an interconnect structure, e.g., interposer has square bond pad, 136 [0033].
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Huang is directed to semiconductor packaging. At annotated Figure 14, Huang teaches an integrated circuit 50 [0016], has square bonding pads 84 [0026], i.e. die interconnect structures are square.
Taken as a whole the prior art is directed to semiconductor packaging. Rubin and Huang teach it is conventional in the art to use square die and interposer bond pads. An artisan would find it useful to utilize known bond pad shapes. An artisan would recognize that when Wirz’s die and/or interposer bond are configured as square as taught by Rubin and Huang that a second cross-sectional area extending in the first direction less than the first cross-sectional area; and the second cross-sectional area is at least equal to the third cross-sectional area.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein a second cross-sectional area extending in the first direction less than the first cross-sectional area; and the second cross-sectional area is at least equal to the third cross-sectional area, to implement conventional bond pads that are square in the xy plane and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 3 which depends upon claim 1, Examiner understands that the device of claim 1 with the plurality of metal interconnects further comprises: a second first pad having a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and the IC package further comprises: a second second pad extending in the first direction and adjacent to the third surface, the second second pad having a fifth cross-sectional area extending in the first direction less than the fourth cross-sectional area; and a second solder joint coupled to the second second pad and a second die interconnect of the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction less than the fourth cross-sectional area, the sixth cross-sectional is less than or equal to the fifth cross-sectional area is a duplication of the interconnect structure of claim 1 and Examiner takes the position that mere duplication of parts has no patentable significance unless and new or unexpected result is obtained, See MPEP 2144.
Regarding claim 4 which depends upon claim 3, Examiner understands that the device of claim 1 wherein the first cross-sectional area is equal to the fourth cross-sectional area, the second cross-sectional area is equal to the fifth cross-sectional area, and the third cross-sectional area is equal to the sixth cross-sectional area perfects the duplication of parts analysis for claim 3 and so has no patentable significance absent a showing of a new or unexpected result, see MPEP 2144.
Regarding claim 5 which depends upon claim 3, Wirz teaches the first pad and the second first pad are coupled in the first direction to form a plane at Figure 2A, i.e. the abut one another.
Regarding claim 10 which depends upon claim 1 Wirz teaches inter alia at [0040], the disclosed package useful for mobile phones.
Accordingly it would have obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the package of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; and a multicopter because Wirz teaches this is a useful application of the package.
Regarding claim 11 and referring to the discussion at claim 1, Wirz teaches and suggests a method for fabricating a substrate, comprising:
forming a die, 126 [0022], comprising a plurality of die interconnects, 110 [0019];
forming a substrate, 126 [0021], comprising a lower metallization layer, 130/112 [0021p22], extending in a first direction, Z direction as annotated, the lower metallization layer comprising a plurality of metal interconnects, 130/112, the plurality of metal interconnects comprising:
a first pad, 130 [0021], having a first surface, as annotated, and a second surface, as annotated, opposite the first surface in a second direction orthogonal to the first direction, as annotated and shown, the first pad having a first cross-sectional area extending in the first direction;
forming a second pad, 112 [0024], coupled to the first surface, as shown, the second pad having a second cross-sectional area extending in the first direction and suggests it is less than the first cross-sectional area; and
coupling a solder joint, 114 [0024-25], to the second pad, as shown, and a first die interconnect, 110, of the plurality of die interconnects, and suggests the first die interconnect having a third cross-sectional area extending in the first direction and suggests it is less than the first cross-sectional area, the second cross-sectional area is at least equal to the third cross-sectional area.
Wirz does not explicitly teach a second cross-sectional area extending in the first direction less than the first cross-sectional area; and the second cross-sectional area is at least equal to the third cross-sectional area, i.e. Wirz does not teach the shapes of the pads and die interconnect structure in the xy plane
Rubin is directed to semiconductor packaging. Rubin teaches at annotated Figure 1B an interconnect structure, e.g., interposer has square bond pad, 136 [0033].
Huang is directed to semiconductor packaging. At annotated Figure 14, Huang teaches an integrated circuit 50 [0016], has square bonding pads 84 [0026], i.e. die interconnect structures are square.
Taken as a whole the prior art is directed to semiconductor packaging. Rubin and Huang teach it is conventional in the art to use square die and interposer bond pads. An artisan would find it useful to utilize known bond pad shapes. An artisan would recognize that when Wirz’s die and/or interposer bond are configured as square as taught by Rubin and Huang that a second cross-sectional area extending in the first direction less than the first cross-sectional area; and the second cross-sectional area is at least equal to the third cross-sectional area.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 10 wherein a second cross-sectional area extending in the first direction less than the first cross-sectional area; and the second cross-sectional area is at least equal to the third cross-sectional area, to implement conventional bond pads that are square in the xy plane and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 12 which depends upon claim 11, Wirz teaches the second cross-sectional area is larger than the third cross-sectional area by an amount to ensure alignment between the solder joint and the second pad, i.e., solder joint is in the correct relative position with respect to the second pad.
Regarding claim 13 which depends upon claim 11, Examiner understands that the method of claim 11 wherein: the plurality of metal interconnects further comprises: a second first pad having a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and the method further comprises: forming a second second pad extending in the first direction and adjacent to the third surface, the second second pad having a fifth cross-sectional area extending in the first direction less than the fourth cross-sectional area; and coupling a second solder joint to the second second pad and a second die interconnect of the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction less than the fourth cross-sectional area, the sixth cross-sectional area matches the fifth cross-sectional area, results in the duplication of the interconnect structure of claim 1 which has not patentable significance absent a showing of a new or unexpected result, see MPEP 2144.
Regarding claim 14 which depends upon claim 13, Examiner understand that the method of claim 13 wherein the first cross-sectional area is equal to the fourth cross-sectional area, the second cross-sectional area is equal to the fifth cross-sectional area, and the third cross-sectional area is equal to the sixth cross-sectional area results from the duplication of the structure produced by the method claim 11 which has no patentable weight absent a showing of a new or unexpected result, see MPEP 2144.
Regarding claim 15 which depends upon claim 13, Wirz teaches the first pad and the second first pad are coupled in the first direction to form a plane, i.e. they abut one another.
Allowable Subject Matter
Claims 2, 6-9 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2 the prior art does not teach the device claim 1, wherein the substrate further comprising: an upper metallization layer extending in the first direction, the upper metallization layer comprising a second plurality of metal interconnects, the second plurality of metal interconnects comprising: a second first pad having a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and wherein the IC package further comprises: a second second pad extending in the first direction and adjacent to the third surface, the second second pad having a fifth cross-sectional area extending in the first direction and less than the fourth cross-sectional area; and a second solder joint coupled to the second second pad and a second die interconnect of the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction and less than the fourth cross-sectional area, the sixth cross-sectional is less than or equal to the fifth cross-sectional area.
Regarding claim 6 the prior art fails to disclose the device claim 1, wherein the second cross-sectional area is equal to or less than 30π square micrometers (μm2).
Regarding claim 7 the prior art fails to disclose the device claim 1, wherein the first die interconnect of the plurality of die interconnects has a first height less than 37 micrometers (μm).
Regarding claim 8 depends upon claim 6 and is allowable on that basis.
Regarding claim 9 depends upon claim 7 and is allowable on that basis.
Regarding claim 16, the prior art fails to teach the method of claim 11 wherein the second cross-sectional area is equal to or less than 30π square micrometers (μm2).
Regarding claim 17 the prior art does not teach the method of claim 11, wherein the first die interconnect of the plurality of die interconnects has a first height less than 37 micrometers (μm).
Regarding claim 18 the prior art does not teach the method of claim 16, wherein the solder joint has a second height of less than 30 μm.
Regarding claim 19 depends upon claim 17, and is allowable on that basis.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893