Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 5, reading on the embodiment of Fig. 9B in the reply filed on 7/27/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/2/2024 and 10/7/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because Fig. 9A reference character “130” has been used to designate both “the gate line isolation structure” (elsewhere designated by 130) and “the first dielectric layer” (elsewhere designated by 140). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because Figs. 5 and 8 appear to have the X and Y axis legend inverted from the directions designated in the other figures of the original disclosure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (US 20200051995 A1).
Regarding claim 1, Tanaka discloses a semiconductor structure (Fig. 20), comprising:
a semiconductor layer (10);
a first stack structure (See annotated figure for stack designation) disposed on the semiconductor layer (vertically “on”) and comprising a plurality of first insulating layers (32) and a plurality of gate line layers (46; [0125]: “word-line-level electrically conductive layers”) disposed alternatively (vertically “alternatively”);
a second stack structure (See annotated figure for stack designation) disposed on a side (top “side”, See annotated figure for direction designation) of the first stack structure away (vertically “away”) from the semiconductor layer and comprising at least one select gate line layer (246; [0125]: “drain-select-level electrically conductive layers”);
a gate line isolation structure (74) penetrating through (completely “through”) the first stack structure and the second stack structure in a direction (vertical “direction”) perpendicular to the semiconductor layer; and
a first dielectric layer (170, Note: the annotation is text-wrapped and appears as 17 over 0) disposed on a side of the second stack structure away from the semiconductor layer (170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written) and in contact (direct “contact”) with the gate line isolation structure, the first dielectric layer covering (directly “covering”) at least part of a surface of the gate line isolation structure (a horizontally-facing “surface”) away from the semiconductor layer (the part of structure 74 contacting 170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written).
Illustrated below is a marked and annotated figure of Fig. 20 of Tanaka.
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Regarding claim 2, Tanaka discloses the semiconductor structure of claim 1 (Fig. 20), further comprising:
a first channel structure (160; [0081]: “word-line-level semiconductor channel portion”) penetrating through (completely “through”) the first stack structure;
a second channel structure (260; [0107]: “drain-select-level semiconductor channel portion”) penetrating through (vertically “through”) the second stack structure and connected with the first channel structure ([0107]: “formed directly on”);
a second dielectric layer (132, Note: the annotation is text-wrapped and appears as 13 over 2) disposed on a side (top “side”, See annotated figure for direction designation) of the first dielectric layer away from the semiconductor layer; and
a first conductive post (one of 86) penetrating through (completely “through”) the second dielectric layer and the first dielectric layer and connected (indirectly physically “connected”) with the second channel structure.
Regarding claim 3, Tanaka discloses the semiconductor structure of claim 2 (Fig. 20), further comprising:
a storage region (100); and
a connection region (300),
wherein the gate line isolation structure includes a first part (See annotated Fig. 18B) located in the storage region, and
wherein the first dielectric layer is located in the storage region (This arrangement is shown in Fig. 20), the first dielectric layer is in contact with the first part (direct “contact” is shown in Fig. 20), and the first dielectric layer covers (partially “covers”) a surface (a horizontally facing “surface”) of the first part away from the semiconductor layer (the part of structure 74 contacting 170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written).
Illustrated below is a marked and annotated figure of Fig. 18B of Tanaka.
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Regarding claim 4, Tanaka discloses the semiconductor structure of claim 3, further comprising:
a second conductive post (another of 86) located in the connection region,
wherein the second conductive post penetrates through the second dielectric layer (completely “through”), the second stack structure (completely “through”), and a part of the first stack structure (partially “through”), and
wherein the second conductive post is connected (directly “connected”) with the gate line layer.
Regarding claim 5, Tanaka discloses the semiconductor structure of claim 4, further comprising:
a third conductive post (76) penetrating through (completely “through”) the second dielectric layer and the first dielectric layer, the third conductive post being connected (indirectly physically “connected”) with the select gate line layer,
wherein the first dielectric layer surrounds (horizontally and partially “surrounds”) the third conductive post and is in contact (indirect “contact”) with the third conductive post, or
wherein there is a first spacing between the first dielectric layer and the third conductive post with a part of the second dielectric layer filled in the first spacing.
Regarding claim 6, Tanaka discloses the semiconductor structure of claim 2 (Fig. 20), further comprising:
a storage region (100); and
a connection region (300),
wherein the first dielectric layer is located in the storage region (This arrangement is shown in Fig. 20) and the connection region (This arrangement is shown in Fig. 20), and
wherein the first dielectric layer covers (partially “covers”) a surface (a horizontally facing “surface”) of the gate line isolation structure away from the semiconductor layer (the part of structure 74 contacting 170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written).
Regarding claim 7, Tanaka discloses the semiconductor structure of claim 6 (Fig. 20), further comprising:
a second conductive post (another of 86) located in the connection region, the second conductive post penetrating through the second dielectric layer (completely “through”), the first dielectric layer (completely “through”), the second stack structure (completely “through”), and a part of the first stack structure (partially “through”), and the second conductive post being connected (directly “connected”) with the gate line layer,
wherein the first dielectric layer further surrounds (horizontally and partially “surrounds”) the second conductive post and is in contact (direct “contact”) with the second conductive post.
Regarding claim 8, Tanaka discloses the semiconductor structure of claim 7 (Fig. 20), further comprising:
a third conductive post (76) penetrating through the second dielectric layer (completely “through”) and the first dielectric layer (completely “through”) and connected (indirectly physically “connected”) with the select gate line layer,
wherein the first dielectric layer surrounds (horizontally and partially “surrounds”) the third conductive post and is in contact (indirect “contact”) with the third conductive post.
Regarding claim 9, Tanaka discloses the semiconductor structure of claim 2 (Fig. 20), wherein the first dielectric layer ([0085]: “a silicon oxide-based dielectric material”) and the second dielectric layer ([0087]: “a dielectric material that is different from the dielectric material of the dielectric etch stop material layer”) have different etch selection ratios under same etch conditions ([0086]: “etch stop material”).
Regarding claim 10, Tanaka discloses the semiconductor structure of claim 1 (Fig. 20), wherein a sidewall of the gate line isolation structure (horizontally facing “sidewall”) is in contact (direct “contact”) with the select gate lines.
Regarding claim 11, Tanaka discloses the semiconductor structure of claim 1 (Fig. 20), wherein the second stack structure further comprises: a third dielectric layer (132, Note: the annotation is text-wrapped and appears as 13 over 2) disposed between (vertically “between”) the select gate line layer and the first dielectric layer and having a etch selection ratio different from that of the first dielectric layer under same etch conditions ([0085]: “a silicon oxide-based dielectric material” in combination with [0087]: “a dielectric material that is different from the dielectric material of the dielectric etch stop material layer” and [0086]: “etch stop material”).
Regarding independent claim 12, Tanaka discloses a method of fabricating a semiconductor structure (Fig. 20), comprising:
forming a first stack structure (See annotated figure for stack designation) and a second stack structure (See annotated figure for stack designation) on a substrate (10), the first stack structure comprising a plurality of first insulating layers (32) and a plurality of gate line layers (46; [0125]: “word-line-level electrically conductive layers”) disposed alternatively (vertically “alternatively”), and the second stack structure comprising at least one select gate line layer (246; [0125]: “drain-select-level electrically conductive layers”);
forming a gate line isolation structure (74) penetrating through (completely “through”) the first stack structure and the second stack structure; and
forming an initial first dielectric layer (170, Note: the annotation is text-wrapped and appears as 17 over 0) on sides of the second stack structure and the gate line isolation structure away from the substrate (170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written), the initial first dielectric layer covering surfaces of the second stack structure (internal “surfaces”) and the gate line isolation structure (a horizontally-facing “surface”) away from the substrate (170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written).
Regarding claim 13, Tanaka discloses the method of claim 12 (Fig. 20), wherein:
the semiconductor structure comprises a storage region (100) and a connection region (300),
the initial first dielectric layer comprises a third part (a portion of 170 within 100) located in the storage region and a fourth part (a portion of 170 within 300) located in the connection region, and
after the forming the initial first dielectric layer (“after” the method step of Fig. 7), the method further comprises:
patterning the initial first dielectric layer (the “patterning” for 86 is shown in the method steps between Figs. 17A and 18A) to remove the fourth part of the initial first dielectric layer (8P occupies a space previously occupied by 170, thus “remove the fourth part” is taught by this method step); and
forming a first avoiding hole (Fig. 10D: hole 149´) in the third part of the initial first dielectric layer with a spacing (horizontal “spacing”) between the first avoiding hole and the gate line isolation structure.
Regarding independent claim 20, Tanaka discloses a three-dimensional memory ([0032]: “three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings”), comprising:
a semiconductor structure (Fig. 20), comprising:
a semiconductor layer (10);
a first stack structure (See annotated figure for stack designation) disposed on the semiconductor layer (vertically “on”) and comprising a plurality of first insulating layers (32) and a plurality of gate line layers (46; [0125]: “word-line-level electrically conductive layers”) disposed alternatively (vertically “alternatively”);
a second stack structure (See annotated figure for stack designation) disposed on a side (top “side”, See annotated figure for direction designation) of the first stack structure away (vertically “away”) from the semiconductor layer and comprising at least one select gate line layer (246; [0125]: “drain-select-level electrically conductive layers”);
a gate line isolation structure (74) penetrating through (completely “through”) the first stack structure and the second stack structure in a direction (vertical “direction”) perpendicular to the semiconductor layer; and
a first dielectric layer (170, Note: the annotation is text-wrapped and appears as 17 over 0) disposed on a side of the second stack structure away from the semiconductor layer (170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written) and being in contact (direct “contact”) with the gate line isolation structure, the first dielectric layer covering (directly “covering”) at least part of a surface of the gate line isolation structure (a horizontally-facing “surface”) away from the semiconductor layer (the part of structure 74 contacting 170 is not directly contacting layer 10, thus it is “away” within the scope of the claim as written); and
a peripheral device ([0053]: “peripheral circuitry”) connected (at least indirectly “connected”) with the semiconductor structure.
Illustrated below are Figs. 10D, 17A, and 18A.
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Allowable Subject Matter
Claims 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 14-16 is the inclusion of the limitation “after the patterning the initial first dielectric layer, the method further comprises: forming a second dielectric layer on sides of the initial first dielectric layer and the second stack structure away from the substrate; forming a first contact hole on the second dielectric layer, the first contact hole penetrating through the second dielectric layer and stopping at the third part of the initial first dielectric layer; extending the first contact hole such that the first contact hole penetrates through the initial first dielectric layer and exposes a surface of the second channel structure away from the substrate; and forming a first conductive post in the first contact hole, the first conductive post being connected with the second channel structure” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “after” and the corresponding method steps arranged in the claimed sequence, in combination with all other limitations in claims 14, 13, and 12. The claimed method steps were found in the prior art but the particularly arranged sequence was not found or suggested by the prior art.
The primary reason for the allowable subject matter of claims 17-19 is the inclusion of the limitation “forming a first contact hole on the second dielectric layer, the first contact hole penetrating through the second dielectric layer and stopping at the initial first dielectric layer; extending the first contact hole such that the first contact hole penetrates through the initial first dielectric layer and exposes a surface of the second channel structure away from the substrate; and forming a first conductive post in the first contact hole, the first conductive post being connected with the second channel structure” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “exposes” and the corresponding method steps arranged in the claimed sequence, in combination with all other limitations in claims 17 and 12. The claimed method steps were found in the prior art but the particularly arranged sequence was not found or suggested by the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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