DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This Office Action is in response to Applicant’s application 18/531,753 filed on March 25, 2026 in which claims 1-14 and 21-26 are pending.
Drawings
The drawings submitted on December 07 2023 have been reviewed and accepted by the Examiner.
Notation
References to patents will be in the form of (C: L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Election/Restrictions
Applicant’s election without traverse of claims 1-14 and 21-26 in the reply filed on March 25 2026 is acknowledged. Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 15-20 are canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Perng et al. (US 11,508,843 B1; herein after “Perng”) in view of Lee et al. (US 2022/0085011 A1; hereinafter “Lee”).
Regarding claim 1, Perng teaches a method for manufacturing a semiconductor device, comprising:
forming a gate oxide layer (18, Fig.21; 5:50-51) over a high-voltage N-type well region (111, Fig.21; 8:40-45), an N-type well region (23, Fig.21; 8:31-33) and a P-type well region (112, Fig.21; 8:30-35), wherein the gate oxide layer (18, Fig.21) comprises a first layer portion (181, Fig.21; 7:56-60) and a second layer portion (182, Fig.21; 7: 56-60), and the first (181) and second layer (182) portions have different thicknesses (182 have different thickness ; Fig.21);
forming a main gate (19’; Fig.21; 8:55-60) on the first layer portion (191) and the second layer portion (192);
forming at least one split gate on the second layer portion (192), wherein the main gate (19’; Fig. 21) and the split gate (191) extend along an interface between the high-voltage N-type well region (111) and the P-type well region (112);
Perng does not tech forming an inter-level dielectric (ILD) layer over the main gate and the split gate; forming a plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate; and forming an electrode to contact the connecting features.
However, Lee teaches forming an inter-level dielectric (ILD) layer (160, Fig. 4; ¶ 0057) over the main gate (GLA) and the split gate (different portions of GLA; ¶ 0031); forming a plurality of connecting features (CB; Fig.4; ¶ 0045) penetrating the ILD layer (160) to contact the main gate (GLA) and the split gate (other portions of GLA); and forming an electrode (184, ¶ 0060) to contact the connecting features (CB).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have an inter-level dielectric (ILD) layer over the main gate and the split gate, forming a plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate, and forming an electrode to contact the connecting features in the device of Perng as taught by Lee for the purpose of connecting the gate of the transistor to different parts of the circuit.
Regarding claim 2, Perng teaches a thickness ratio of the second layer portion to the first layer portion is greater than 3.
However, Perng teaches the thickness ratio of the second layer (182. Fig.21) is at least 2.0 to 2.5 times (5:55-57).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have teaches a thickness ratio of the second layer portion to the first layer portion is greater than 3 in the device of Perng since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Regarding claim 3, Perng teaches forming a source region (22, Fig.21; 8:33-35) in the P-type well region (112); and forming a drain region (23, Fig.21; 8:33-35) in the N-type well region (111).
Regarding claim 4, Perng teaches the first layer (181, Fig. 21) portion overlaps the interface between the high-voltage N-type well region (111) and the P-type well region (112), and the second layer (182) portion overlaps an interface between the high-voltage N-type well region (111) and the N-type well region (23).
Regarding claim 5, Perng teaches the first layer (181, Fig. 21) portion overlaps the interface between the high-voltage N-type well region (111) and the P-type well region (112).
Regarding claim 10, Perng teaches wherein the first layer portion is an input/output (I/O) oxide layer portion (181) and the second layer portion is a reduced surface field oxide (ROX) layer portion (182; Fig.21; 5: 50-55), and a width of the second layer portion is greater than a width of the first layer portion in a direction perpendicular to the interface between the high-voltage N-type well region and the P-type well region (width of 182 is greater than the width of 181 in a direction of Y-axis wherein the interface is in the X-direction; Fig.21).
Regarding claim 21, Perng teaches a method for manufacturing a semiconductor device, comprising:
forming an N-type well region (23, Fig.21; 8:31-33) in a substrate (11, Fig.21; 25-30)
forming a P-type well region (112, Fig.21; 8:35-40) in the substrate (11);
forming a high-voltage well region (111, Fig.21; 8:40-45) in the substrate and between the N-type well region (23) and the P-type well region (112);
forming a gate oxide layer (18, Fig.21; 5:50-51) over the substrate (11), wherein the gate oxide layer (118) comprises a reduced surface field oxide (ROX) layer portion (182, Fig.21; 7:56-60) on the N-type well region (23) and the high-voltage well region (111), and an input/output (I/O) oxide layer portion (181, Fig.21; 7:55-60) on the high-voltage well region (1112) and the P-type well region (24), wherein the ROX layer (182) portion is thicker than the I/O oxide layer portion (181);
forming a main gate (19’, Fig.218:55-60) on the I/O oxide portion (181) and the ROX layer potion (182);
forming a plurality of split gates (191 and 192; 7:55-60) on the ROX layer portion (182).
Perng does not teach forming an inter-level dielectric (ILD) layer over the main gate and the split gates; forming a first connecting features penetrating the ILD layer to contact the main gate; forming a plurality of second connecting features penetrating the ILD layer to contact the split gates; and forming a metal line over the ILD layer to contact first and second connecting features, wherein the first connecting feature is thicker than the second connecting features.
However, Lee teaches forming an inter-level dielectric (ILD) layer (160, Fig. 4; ¶ 0057) over the main gate (GLA) and the split gate (different portions of GLA; ¶ 0031); forming a first connecting features (CB; Fig.4; ¶ 0045) penetrating the ILD layer (160) to contact the split gates (other portions of GLA); forming a plurality of second connecting features (CBH; Fig.4) penetrating the ILD layer (160) to contact the split gates and forming a metal line (184; ¶ 0060) over the ILD layer (160) to contact the split gates (GLA) and forming a metal line (186, Fig.4; ¶0045) over the ILD layer (160) to contact first (CB) and second connecting features (CBH), wherein the first connecting feature (CB) is thicker than the second connection features (CBH).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have an inter-level dielectric (ILD) layer over the main gate and the split gate; forming a plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate; and forming an electrode to contact the connecting features in the device of Perng as taught by Lee for the purpose of connecting the gate of the transistor to different parts of the circuit.
Regarding claim 22, Perng teaches forming a source region (22, Fig.21; 8:33-35) in the P-type well region (112); and forming a drain region (23, Fig.21; 8:33-35) in the N-type well region (111).
Regarding claim 23, Perng teaches a thickness ratio of the second layer portion to the first layer portion is greater than 3.
However, Perng teaches the thickness ratio of the second layer (182. Fig.21) is at least 2.0 to 2.5 times (5:55-57).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have teaches a thickness ratio of the second layer portion to the first layer portion is greater than 3 in the device of Perng since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Regarding claim 25, Perng teaches the main gate (19’; Fig. 21) and the split gate (191) extend along an interface between the high-voltage N-type well region (111) and the P-type well region (112).
Claims 6, 7, 11-13, 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Perng et al. (US 11,508,843 B1; herein after “Perng”) in view of Lee et al. (US 2022/00850 A1; hereinafter “Lee”) as applied to claim 1 and 21, and further in view of Xu et al. (US 2023/0343869 A1; in view of “Xu”).
Regarding claims 6 and 24, Perng as modified by Lee does not teach the main gate and the split gate have the same thickness.
However, Xu teaches the main gate (216; Fig.3; ¶ 0060) and the split gate (212; Fig.3; ¶ 0060) have the same thickness (216 and 212 have the same thickness).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have the main gate and the split gate have the same thickness in the device of Perng and Lee as taught by Xu since the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Regarding claims 7 and 26, Perng as modified by Lee does not teach wherein a width of the main gate is greater than a width of the split gate in a direction perpendicular to the interface between the high-voltage N-type well region and the P-type well region.
However, XU teaches a width of the main gate is greater than a width of the split gate in a direction perpendicular to the interface between the high-voltage N-type well region and the P-type well region (the width of 216 at the C-C is greater than the width of 212 between the C-C and B-B as shown in Figure 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have the main gate is greater than a width of the split gate in a direction perpendicular to the interface between the high-voltage N-type well region and the P-type well region since the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Regarding claim 11, Perng as modified by Lee does not teach a width of the main gate overlapping the first layer portion is greater than a width of the main gate overlapping the second layer portion in a direction perpendicular to the interface between the high-voltage N-type well region and the P-type well region.
However, Xu teaches a width of the main gate (216 and 212 at the CC line, Fig.2) overlapping the first layer portion (214) is greater than a width of the main gate (216 formed at the BB line; Fig.2) overlapping the second layer portion (218, Fig.2-3) in a direction perpendicular to the interface between the high-voltage N-type well region (206) and the P-type well region (204).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a width of the main gate overlapping the first layer portion is greater than a width of the main gate overlapping the second layer portion in a direction perpendicular to the interface between the high-voltage N-type well region and the P-type well region in the device of Perng and Lee as taught by Xu since the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Regarding claim 12, Perng teaches a method for manufacturing a semiconductor device, comprising:
forming an N-type well region (23, Fig.21; 8:31-33) in a substrate (11, Fig.21; 25-30)
forming a P-type well region (112, Fig.21; 8:35-40) in the substrate (11);
forming a high-voltage well region (111, Fig.21; 8:40-45) in the substrate and between the N-type well region (23) and the P-type well region (112);
forming a gate oxide layer (18, Fig.21; 5:50-51) over the substrate (11), wherein the gate oxide layer (118) comprises a reduced surface field oxide (ROX) layer portion (182, Fig.21; 7:56-60) on the N-type well region (23) and the high-voltage well region (111), and an input/output (I/O) oxide layer portion (181, Fig.21; 7:55-60) on the high-voltage well region (1112) and the P-type well region (24);
forming a main gate (19’, Fig.218:55-60) and a plurality of split gates (191 and 192; 7:55-60) on the gate oxide layer (118), and the split gates (192) overlap the ROX layer portion (182).
Perng does not teach wherein the main gate overlaps the ROX layer portion and the I/O oxide layer portion and forming an interconnection structure over the main gate and the split gates, wherein the main gate is electrically connected to the split gates through the interconnection structure.
However, Lee teaches forming an interconnection structure (CB; Fig.4; ¶ 0045) over the main gate (GLA) and the split gate (other portions of GLA); wherein the main gate (GLA) is electrically connected to the split gates through the interconnect structure (CB).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have an inter-level dielectric (ILD) layer over the main gate and the split gate; forming a plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate; and forming an electrode to contact the connecting features in the device of Perng as taught by Lee for the purpose of connecting the gate of the transistor to different parts of the circuit.
However, Xu teaches a similar device in the same field of endeavor (Figure 2) and the main gate (216, Fig.2; ¶ 0060) overlaps the ROX layer portion (218, Fig.6D; ¶0060) and the I/O oxide layer portion (portion of 214; Fig. 6D).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have the main gate overlaps the ROX layer portion and the I/O oxide layer portion in the device of Perng and Lee as taught by Xu to modulate an electric field in the LDMOS device which increases the breakdown voltage of the device (¶ 0050).
Regarding claim 13, Perng teaches a thickness ratio of the second layer portion to the first layer portion is greater than 3.
However, Perng teaches the thickness ratio of the second layer (182. Fig.21) is at least 2.0 to 2.5 times (5:55-57).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have teaches a thickness ratio of the second layer portion to the first layer portion is greater than 3 in the device of Perng since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Allowable Subject Matter
Claims 8, 9 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 is objected to since the prior art does not teach the following limitations: “forming the high-voltage N-type well region, the N-type well region and the P-type well region in a substrate, wherein bottom surfaces of the high-voltage N-type well region, the N-type well region and the P-type well region are at the same level.”
Claim 9 is objected to since the prior art does not teach the following limitations “…wherein forming the connecting features penetrating the ILD layer to contact the main gate and the split gate further comprises: forming a first connecting feature to contact the main gate overlapping the first layer portion; and forming a second connecting feature to contact the split gate, wherein the first connecting feature is thicker than the second connecting feature.”
Claim 14 is objected to since the prior art does not teach the following limitations : “..]an epitaxial layer underneath the high-voltage well region, the P-type well region and the N-type well region; forming a buried oxide layer underneath the epitaxial layer; forming an isolation region penetrating the P-type well region, the epitaxial layer and the buried oxide layer; and forming a connecting feature penetrating the isolation region to contact the substrate underneath the buried oxide layer.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
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/Mounir S Amer/Primary Examiner, Art Unit 2818