Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 12/07/23. Claims 1-20 are pending in this application.
Claim Rejections under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 11, 12, 14-17 are rejected under 35 U.S.C. §102(a)(1) as being unpatentable over Hua (CN 114121961 A).
Regarding claim 1, Hua discloses a method for manufacturing a semiconductor structure, comprising:
forming a first base (see fig 14/15 disclosing 121), wherein the first base comprises a first substrate and active areas 103 arranged in an array (see devices in figs 14 and 15 arranged in array) along a first direction and a second direction in the first substrate(see fig 14 and 15 disclosing array formed across the page perpendicular to substrate), word lines are disposed in the first base (see gates 112 being word lines), and the word lines extend along the second direction and cover at least opposite sides of each of the active areas (see fig 14 and 15, disclosing 112 extending into the page);
forming charge storage structures on the first base (see 118), wherein the charge storage structures are electrically connected with first ends of the active areas (see 118 connected to 105 via 117);
forming a second base (see fig 17, disclosing 200 connected with 124 with 121 and 122), wherein the second base comprises a second substrate and bit lines disposed in the second substrate(see fig 17, disclosing 124 as second base with fill layer surrounding 121 and 122), the bit lines extend along the first direction (see fig 17, disclosing into the page); and connecting the first base and the second base by using a first surface of the first base away from the charge storage structures (see 124 is attached to backside/opposite side of 200)and a second surface of the second base having structures of the bit lines as connection surfaces (see 121 connected to 120), wherein the bit lines are electrically connected with second ends of the active areas(see fig 17, disclosing 120/212 connection); and each of the first ends is disposed opposite to a corresponding one of the second ends(see 200 is opposite to 124).
Regarding claim 2, Hua discloses the method for manufacturing the semiconductor structure of claim 1, wherein connecting the first base and the second base further comprises: connecting the first base and the second base through a bonding process.1
Regarding claim 3, Hua discloses the method for manufacturing the semiconductor structure of claim 2, wherein before connecting the first base and the second base, the method further comprises: thinning the first base to expose the second ends of the active areas (see claim 29 disclosing thinning to expose contact surfaces).
Regarding claim 6, Hua discloses the method for manufacturing the semiconductor structure of claim 2, wherein the operation of connecting the first base and the second base through the bonding process comprises: forming first contact structures on the first surface of the first base (see fig 17, disclosing 122 connecting 120), the first contact structures being electrically connected with the second ends of the active areas (105 connects to 120); forming second contact structures on the second surface of the second base(see 122 on lower substrate), the second contact structures being electrically connected with the bit lines (see fig 7 disclosing connection); and bonding by using the first contact structures and the second contact structures as bonding structures.2
Regarding claim 7, Hua discloses the method for manufacturing the semiconductor structure of claim 6, wherein the operation of forming the first contact structures on the first surface of the first base comprises: forming a first contact layer on the first surface of the first base (see 120), wherein the first contact layer comprises a first filling layer and the first contact structures disposed in the first filling layer (see 102 is filled); the operation of forming the second contact structures on the second surface of the second base comprises: forming a second contact layer on the second surface of the second base (see formation of 122), wherein the second contact layer comprises a second filling layer and the second contact structures disposed in the second filling layer (see 122 is formed in 124); and the operation of bonding by using the first contact structures and the second contact structures as the bonding structures comprises: bonding by using the first contact layer and the second contact layer as bonding layers (see fig 7),3 wherein the first filling layer is bonded with the second filling layer, and the first contact structures are bonded with the second contact structures.4
Regarding claim 8, Hua discloses the method for manufacturing the semiconductor structure of claim 1, wherein after forming the charge storage structures, the method further comprises: forming a first interlayer dielectric layer which covers surfaces of the charge storage structures and a surface of the first base (see fig 17 disclosing 118 connected via 117); and after connecting the first base and the second base (see fig 17, disclosing the two bases together), the method further comprises: forming word line lead-out structures (see 112), bit line lead-out structures (see 112), and charge storage lead-out structures at a side of the first base away from the second base (118); wherein the word line lead-out structures penetrate the first interlayer dielectric layer and are electrically connected with the word lines (see figs see 126), the bit line lead-out structures penetrate the first interlayer dielectric layer and the first base and are electrically connected with the bit lines (see figs 1, 9, 10, 18), and the charge storage lead-out structures penetrate the first interlayer dielectric layer and are electrically connected with the charge storage structures(see figs 1, 9, 10, 18).
Regarding claim 11, Hua discloses the method for manufacturing the semiconductor structure of claim 1, wherein the operation of forming the word lines in the first base comprises: forming word line trenches arranged at intervals in the first base (see figs 5-8); filling a word line material in the word line trenches (see figs 5-8); forming the word lines by removing part of the word line material and retaining at least the word line material on opposite sides of the active areas(see figs 5-8 disclosing leaving a portion of the word line in place); and forming a first isolation layer between two adjacent word lines of the word lines (see figs 5-8).
Regarding claim 12, Hua discloses the method for manufacturing the semiconductor structure of claim 1, wherein before forming the charge storage structures on the first base, the method further comprises: forming capacitor connection structures on the first base (see fig 14. Where 119 is connected), wherein the capacitor connection structures are electrically connected with the first ends of the active areas (see fig 14).
Regarding claim 14, Hua discloses the method for manufacturing the semiconductor structure of claim 1, wherein the operation of forming the second base comprises: forming bit line trenches in the second substrate (see figs 16 and 17 disclosing formation of second substrate); forming a second isolation layer covering an inner wall of each of the bit line trenches in the bit line trenches(formation of 124 surrounding 122, trenches run laterally, as shown in fig18); and forming a bit line in each of the bit line trenches, wherein the second isolation layer is disposed between the bit line and the second substrate (see formation of 122).
Regarding claim 15, Hua discloses a semiconductor structure, comprising:
a first base (see fig 14), wherein the first base comprises a first substrate and active areas arranged in an array along a first direction and a second direction in the first substrate(see fig 14 and 15 disclosing array formed across the page perpendicular to substrate), word lines are disposed in the first base (see gates 112 being word lines), and the word lines extend along the second direction and cover at least opposite sides of each of the active areas (see fig 14 and 15, disclosing 112 extending into the page);
a charge storage structures on the first base (see 118), wherein the charge storage structures are electrically connected with first ends of the active areas (see 118 connected to 105 via 117);
a second base (see fig 17, disclosing 124 with 121 and 122), wherein the second base comprises a second substrate and bit lines disposed in the second substrate(see fig 17, disclosing 124 with 121 and 122), the bit lines extend along the first direction (see fig 17, disclosing into the page); and connecting the first base and the second base by using a first surface of the first base away from the charge storage structures (see 124 is attached to backside/opposite side of 200)and a second surface of the second base having structures of the bit lines as connection surfaces (see 121 connected to 120), wherein the bit lines are electrically connected with second ends of the active areas(see fig 17, disclosing 120/212 connection); and each of the first ends is disposed opposite to a corresponding one of the second ends(see 200 is opposite to 124).
Regarding claim 16, Hua discloses the semiconductor structure of claim 15, wherein the first base has a first surface (see fig 16, 17, disclosing 124/122 having tops and bottoms), and the first surface has first contact structures electrically connected with the second ends of the active areas (see fig 17 where the substrates are connected together); the second base has a second surface opposite the first surface (see fig 17), the second surface has second contact structures electrically connected with the bit lines and the first contact structures (see 122 in second substrate connecting to first substrate).
Regarding claim 17, Hua discloses the semiconductor structure of claim 16, further comprising: a first filling layer disposed on the first surface and a second filling layer disposed on the second surface (see filling layers 124/420), wherein the first contact structures are disposed in the first filling layer, the second contact structures are disposed in the second filling layer (see fig 17 where layers contact), and the first filling layer is connected with the second filling layer (see fig 17, where 124 contacting 120).
Allowable Subject Matter
Claim 4 recites allowable subject matter. In particular, the cited art do not disclose a plasma treatment that treats surfaces of the first and second substrate. Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 5 depends from claim 4 and is allowable
Claims 9, 10 recite allowable subject matter. In particular, the cited art do not disclose wherein the semiconductor structure comprises a core region and a periphery region, the word lines, the bit lines and the charge storage structures are located in the core region; during the operation of forming the first base, word line connection structures are formed in the periphery region and are electrically connected with the word lines; during the operation of forming the second base, bit line connection structures are formed in the periphery region and are electrically connected with the bit lines; and during the operation of forming the word line lead-out structures, the bit line lead-out structures, and the charge storage lead-out structures at the side of the first base away from the second base, the word line lead-out structures are formed in the periphery region and are electrically connected with the word line connection structures, the bit line lead-out structures are formed in the periphery region and are electrically connected with the bit line connection structures, and the charge storage lead-out structures are formed in the core region, as recited in claim 9.
The cited art do not disclose wherein after forming the first interlayer dielectric layer, the method further comprises: provide a third base; and connecting the third base and the first base by using a surface of the first interlayer dielectric layer as a connection surface; and wherein before forming the word line lead-out structures, the bit line lead-out structures, and the charge storage lead-out structures at the side of the first base away from the second base, the method further comprises: removing the third base, as recited in claim 10. Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 contain allowable subject matter. Claims 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
1 Hua discloses an embodiment wherein: a third isolation layer 123 located on the first surface 101, wherein the third isolation layer 123 covers a plurality of the capacitor structures 118; and a second substrate 200 bonded to the third isolation layer 123.
2 Ibid.
3 Ibid.
4 Ibid.
Prosecution Insights