Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The independent claims are 1, 13, 17.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation “the solder layer” and "the solder paste" in the limitation “wherein the solder layer provided on the exterior of the connection pin and the solder paste provided on the first connection surface have the same composition”. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, claim 16 is interpreted to include the limitations in both claim 14 and 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 8-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (hereinafter Lee, US 2022/0384320) in view of Kawasaki et al. (hereinafter Kawasaki, US 2017/0287862).
In regards to independent claim 1, Lee teaches a semiconductor package comprising:
a semiconductor chip (Lee, Fig. 1 Item 140, [0023], “semiconductor chip”);
a first connector (100) mounted on a first surface of the semiconductor chip (Lee, [0033], “The semiconductor chip 140 may be mounted on the package substrate 100”) and having a first connection surface (Lee, Fig. 1 upper pads, [0034], “a plurality of upper pads (e.g., first to third upper pads 126, 127, and 128) disposed on an upper surface of the substrate base 110”);
a second connector (170) having a second connection surface (Lee, Fig. 1 Item 175, [0041], “The plurality of lower pads (e.g., first and second lower pads 175 and 176) may be disposed on a lower surface of the base insulating layer 171.”); and
a connection pin (160), wherein the first end of said connection pin electrically connects to said first connection surface and the second end of said connection pin electrically connects to said second connection surface (Lee, Fig. 1 Item 160, “Each of the first lower pads 175 may be connected to a corresponding one of the first upper pads 126 through the conductive connectors 160”),
Lee fails to explicitly teach:
a connection pin with an aspect ratio (length/diameter) of 1 to 10
wherein a solder joint is provided between said first connection surface and said first end of the connection pin.
Kawasaki teaches:
a connection pin with an aspect ratio (length/diameter) of 1 to 10 (Kawasaki, [0055], “diameter φ of each of the top and bottom surfaces of the Cu column 1 according to the present invention is…more preferably 1-300 μm... Also, a height L of the Cu column 1 is preferably 1-3000 μm”),
wherein a solder joint is provided between said first connection surface and said first end of the connection pin (Kawasaki, [0062], “The Cu column 1 or the Cu core column 3 according to the present invention can be used for forming a solder joint connecting the electrodes. In this embodiment, for example, a structure in which the solder bump is mounted on the electrode of the printed circuit board is referred to as a solder joint. A solder bump is a structure in which the Cu column 1 is mounted on the electrode of the semiconductor chip”).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kawasaki before him before the effective filing date of the claimed invention, to modify the conductive connectors taught by Lee to include the Cu column with solder joint of Kawasaki in order to obtain conductive conductors that are Cu columns with solder joints. One would have been motivated to make such a combination because it increases the reliability of the TCT (Temperature Cycling Test) on the connection.
In regards to dependent claim 2, Lee teaches the semiconductor package of claim 1, wherein the tilting angle formed by the connection pin and the first connection surface is 4° or less (Lee, 160 has an incline of 0).
In regards to dependent claim 4, Kawaskai teaches the semiconductor package of claim 1, wherein the solder joint is formed from a solder layer on the exterior of the connection pin that solidifies after melting (Kawasaki, [0058]).
In regards to dependent claim 5, Kawaskai teaches the semiconductor package of claim 4, wherein the solder joint solidifies after melting from a solder paste provided on the first connection surface (Kawasaki, [0058]).
In regards to dependent claim 8, Lee teaches the semiconductor package of claim 1, further comprising a solder bump provided on the lower surface of the semiconductor chip for electrical connection, which connects to the first connection surface (Lee, 131).
In regards to dependent claim 9, Lee teaches the semiconductor package of claim 8, further comprising an underfill between the semiconductor chip and the first connector (Lee, [0038]).
In regards to dependent claim 10, Lee teaches the semiconductor package of claim 9, wherein a solder bump is provided on the upper surface of the semiconductor chip that connects to the second connection surface (Lee, 131, Note: first and second connection surface would be flipped in the independent claim in this instance), and the lower surface of the semiconductor chip is adhered to the first connection surface using an adhesive (Lee, 180, [0060]).
In regards to dependent claim 11, Kawasaki teaches the semiconductor package of claim 1, wherein the solder bump provided on the lower surface of the semiconductor chip comprises a second connection pin with an aspect ratio (length/diameter) of 1 to 10 (Kawasaki, [0055], “diameter φ of each of the top and bottom surfaces of the Cu column 1 according to the present invention is…more preferably 1-300 μm... Also, a height L of the Cu column 1 is preferably 1-3000 μm”),
In regards to dependent claim 12, Lee teaches the semiconductor package of claim 1, wherein at least two semiconductor chips are stacked (Lee, Fig. 11, 310 and 140).
In regards to independent claim 13, Lee teaches a semiconductor package comprising:
a semiconductor chip (Lee, Fig. 1 Item 140, [0023], “semiconductor chip”);
a first connector (100) having a first connection surface to which a terminal of the semiconductor chip connects (Lee, Fig. 1 upper pads, [0034], “a plurality of upper pads (e.g., first to third upper pads 126, 127, and 128) disposed on an upper surface of the substrate base 110”);
a connection pin (131), wherein the first end of said connection pin electrically connects to said first connection surface and the second end of said connection pin electrically connects to a terminal of the semiconductor chip (Lee, Fig. 1 [0037], “The chip pads 141 of the semiconductor chip 140 may be electrically connected to the second upper pads 127 through the chip connection bumps 131”),
Lee fails to explicitly teach:
a connection pin with an aspect ratio (length/diameter) of 1 to 10;
wherein a solder joint is provided between said first connection surface and said first end of the connection pin;
Kawasaki teaches:
a connection pin with an aspect ratio (length/diameter) of 1 to 10 (Kawasaki, [0055], “diameter φ of each of the top and bottom surfaces of the Cu column 1 according to the present invention is…more preferably 1-300 μm... Also, a height L of the Cu column 1 is preferably 1-3000 μm”),
wherein a solder joint is provided between said first connection surface and said first end of the connection pin (Kawasaki, [0062], “The Cu column 1 or the Cu core column 3 according to the present invention can be used for forming a solder joint connecting the electrodes. In this embodiment, for example, a structure in which the solder bump is mounted on the electrode of the printed circuit board is referred to as a solder joint. A solder bump is a structure in which the Cu column 1 is mounted on the electrode of the semiconductor chip”).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kawasaki before him before the effective filing date of the claimed invention, to modify the conductive connectors taught by Lee to include the Cu column with solder joint of Kawasaki in order to obtain conductive conductors that are Cu columns with solder joints. One would have been motivated to make such a combination because it increases the reliability of the TCT (Temperature Cycling Test) on the connection.
In regards to dependent claim 14, Kawasaki teaches wherein the solder joint comprises a solidified material formed from a solder layer on the exterior of the connection pin after melting (Kawasaki, [0058]).
In regards to dependent claim 15, Kawasaki teaches wherein the solder joint comprises a solidified material formed from a solder paste provided on the first connection surface after melting (Kawasaki, [0063]).
In regards to dependent claim 16, Kawasaki teaches wherein the solder layer provided on the exterior of the connection pin and the solder paste provided on the first connection surface have the same composition (Kawasaki, [0058]).
In regards to independent claim 17, Lee teaches a method for manufacturing a semiconductor package, the method comprising the steps of:
providing a first connector (100) with a first connection surface (Lee, Fig. 1 Item 126, [0025], “a plurality of upper pads (e.g., first to third upper pads 126, 127, and 128) disposed on an upper surface of the substrate base 110”);
connecting a first end and a second end of a connection pin to the first connection surface (Lee, Fig. 1 Item 160, “Each of the first lower pads 175 may be connected to a corresponding one of the first upper pads 126 through the conductive connectors 160”);
attaching a semiconductor chip to the first connector (Lee, Fig. 1 Item 140, [0023], “semiconductor chip,” [0033], “The semiconductor chip 140 may be mounted on the package substrate 100”);
filling around the semiconductor chip with resin for protection (Lee, Fig. 1 180, [0060], “the insulating filler 180 may include an epoxy-group molding resin or a polyimide-group molding resin”);
providing a second connector (170) with a second connection surface opposite the first connector (Lee, Fig. 1 Item 175, [0041], “The plurality of lower pads (e.g., first and second lower pads 175 and 176) may be disposed on a lower surface of the base insulating layer 171.”);
connecting a second end of the connection pin to the second connection surface (Lee, Fig. 1 Item 160, “Each of the first lower pads 175 may be connected to a corresponding one of the first upper pads 126 through the conductive connectors 160”).
Lee fails to expllcitly teach:
a connection pin with an aspect ratio (length/diameter) of 1 to 10
Kawasaki teaches a connection pin with an aspect ratio (length/diameter) of 1 to 10 (Kawasaki, [0055], “diameter φ of each of the top and bottom surfaces of the Cu column 1 according to the present invention is…more preferably 1-300 μm... Also, a height L of the Cu column 1 is preferably 1-3000 μm”).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kawasaki before him before the effective filing date of the claimed invention, to modify the conductive connectors taught by Lee to include the Cu column with solder joint of Kawasaki in order to obtain conductive conductors that are Cu columns with solder joints. One would have been motivated to make such a combination because it increases the reliability of the TCT (Temperature Cycling Test) on the connection.
In regards to dependent claim 18, Lee teaches wherein the first connector is selected from one of a PCB, interposer, RDL, or flexible board of the semiconductor package, and the connection surface is one of an electrode, pad, terminal, wiring, or bump provided on the connector (Lee, 126 “upper pad”, 100 substrate PCB [0025]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kawasaki and Chen et al. (hereinafter Chen, US 2019/0189837),
In regards to dependent claim 3, Lee fails to expliclity teach wherein the surface roughness of the connection pin is between RMS 0.5 and 1 μm. Chen teaches wherein the surface roughness of the connection pin is between RMS 0.5 and 1 μm (Chen, [0032]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kawasaki and Chen before him before the effective filing date of the claimed invention, to modify the conductive connectors taught by Lee to include the Cu surface roughness of Chen in order to obtain conductive conductors that are Cu columns with low surface roughness. One would have been motivated to make such a combination because it reduces the resistivity of the connection thereby reducing power loss.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kawasaki and Takagi et al. (hereinafter Takagi, JP 2022080429)
In regards to dependent claim 6, Lee fails to expliclity teach wherein the melting rate of the solder paste is 99% or more. Takagi teaches wherein the melting rate of the solder paste is 99% or more (Takagi, “More preferably, the solder paste has a melting rate of 90% or more at 190 ° C. and / or a melting rate of 98% or more at 195 ° C. It will have components that remain without thermal melting during preheating (150 to 180 ° C), while it will completely melt during thermal melting (220 to 260 ° C) of the solder alloy heated at 220 to 260 °”).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kawasaki and Takagi before him before the effective filing date of the claimed invention, to modify the conductive connectors taught by Lee to include the completely melted solder of Takagi in order to obtain conductive conductors that are Cu columns with completely melted solder. One would have been motivated to make such a combination because it prevents voids thereby reducing resistance.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kawasaki and Shiraishi et al. (hereinafter Shiraishi, US 2020/0398383)
In regards to dependent claim 7, Lee fails to expliclity teach wherein the void content within the solder joint is 10% or less. Shiraishi teaches wherein the void content within the solder joint is 10% or less (Shiraishi, [0009]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Kawasaki and Shiraishi before him before the effective filing date of the claimed invention, to modify the conductive connectors taught by Lee to include the low void content solder of Shiraishi in order to obtain conductive conductors that are Cu columns with low void content solder. One would have been motivated to make such a combination because it prevents an incline in the Cu column by reducing the likelihood of voids.
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812