DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 12-17, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2023/0369476 A1, not that Lin is published on November 16, 2023 and thus considered an intervening reference to the present application that has a foreign priority date of January 27, 2023 with a US filing date of December 7, 2023, therefore, until a certified English translation is submitted to perfect priority see MPEP 216, this reference is considered a 35 U.S.C. 102(a)(1) reference).
With respect to claim 1, Lin discloses, in Figs.1-8, a semiconductor device comprising: a substrate (102) having a recessed region (504) (see Par.[0074] wherein in the example shown in FIG. 5B, the trench 504 is formed by etching the semiconductor substrate 102); a first semiconductor region (108) including a first semiconductor layer (108a) on a bottom surface and an inner side surface of the recessed region and a first protrusion (108b) on an upper surface of the first semiconductor layer (108a), and having a first conductivity type/(P type) (see Par.[0045]-[0047] wherein the collector region 108 is disposed on the high thermal conductivity region 106; the collector region 108 includes a bottom portion 108a and a sidewall portion 108b; the bottom portion 108a extends in the horizontal plane (i.e., the X-Y plane as shown in FIG.1); the collector region 108 is p-type and heavily doped (i.e., p+)); a second semiconductor region (110) including a second semiconductor layer (110a) on the first semiconductor layer (108a) in the recessed region (504) and a second protrusion (110b) on an upper surface of the second semiconductor layer (108b), and having a second conductivity type/(N type) (see Par.[0049]-[0054] wherein the buffer region 110 is disposed on the collector region 108; the buffer region 110 includes a bottom portion 110a and a sidewall portion 110b; the bottom portion 110a extends in the horizontal plane (i.e., the X-Y plane as shown in FIG. 1); the bottom portion 110a is disposed on the bottom portion 108a of the collector region 108; the buffer region 110 is of the second conductive type opposite to the first conductive type and heavily doped); a third semiconductor region (114) including a third semiconductor layer (114) on the second semiconductor layer (110a) in the recessed region (504) and a third protrusion/(vertical portion 114) on an upper surface of the third semiconductor layer (114), and having the first conductivity type/(P type) (see Par.[0054]-[0055] wherein the body region 114 is of the first conductive type and lightly doped. In the example shown in FIGS. 1A-1C, the body region 114 is p-type and lightly doped (i.e., p−); the body region 114 serves as the body of the first MOSFET and the drain of the second MOSFET); an epitaxial stopper layer (106) covering the bottom surface of the recessed region (504) between the first semiconductor region (108) and the substrate (102), and including a material different from materials of the first to third semiconductor regions (see Par.[0033] wherein in FIGS. 1A-1C, the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112; see Par.[0041]-[0042] wherein the thermal conductivity of the high thermal conductivity region 106 is larger than 4 W/cm.Math.K; since the high thermal conductivity region 106 has a high thermal conductivity and a large contact area with the collector region 108 due to the non-planar structure of the high thermal conductivity region 106, the large amount of heat generated during the operation of the IGBT 100 can be dissipated or removed faster through the high thermal conductivity region 106; the high thermal conductivity region 106 is made of a silicon compound; the high thermal conductivity region 106 is made of silicon carbide (SiC); see Par.[0030] wherein the high thermal conductivity region is introduced using epitaxial growth of a silicon epitaxial layer, during which carbon is used as a material source as well); and a dummy gate structure (122) on at least one of the first to third protrusions on the substrate (102) (see Par.[0033] wherein in FIGS. 1A-1C, the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112, a body region 114, two source regions 116a and 116b, an emitter electrode 118, two gate dielectric structures 120a and 120b, two gate electrodes 122a and 122b, and two collector electrodes 124a and 124b).
With respect to claim 2, Lin discloses, in Figs.1-8, the semiconductor device, wherein an entirety of the third semiconductor region (114) overlaps the first and second semiconductor regions (108 and 110) and the epitaxial stopper layer (106) in a direction perpendicular to an upper surface of the substrate (102) (see Fig.1D).
With respect to claim 3, Lin discloses, in Figs.1-8, he semiconductor device, wherein in a plan view, the first semiconductor region (108) surrounds the second semiconductor region (110) and the second semiconductor region (110) surrounds the third semiconductor region (114) (see Fig.1D).
With respect to claim 4, Lin discloses, in Figs.1-8, the semiconductor device, wherein in the plan view, the epitaxial stopper layer (106) surrounds the first semiconductor region (108) (see Fig.1D).
With respect to claim 5, Lin discloses, in Figs.1-8, the semiconductor device, wherein the epitaxial stopper layer (106) includes at least one of SiGe, Si:C, Si:As, and SiGe:C (see Par.[0041]-[0042] wherein the thermal conductivity of the high thermal conductivity region 106 is larger than 4 W/cm.Math.K; since the high thermal conductivity region 106 has a high thermal conductivity and a large contact area with the collector region 108 due to the non-planar structure of the high thermal conductivity region 106, the large amount of heat generated during the operation of the IGBT 100 can be dissipated or removed faster through the high thermal conductivity region 106; the high thermal conductivity region 106 is made of a silicon compound. In one example, the high thermal conductivity region 106 is made of silicon carbide (SiC)).
With respect to claim 6, Lin discloses, in Figs.1-8, the semiconductor device, wherein each of the first to third semiconductor regions is formed of an epitaxial layer (see Par.[0048] wherein a silicon epitaxial layer can be formed on the high thermal conductivity region 106 before the collector region 108 is formed thereon; the high thermal conductivity region 106 and the collector region 108 sandwich a silicon epitaxial layer; see Par.[0079]-[0080] wherein the first silicon epitaxial layer 508 is formed on the oxygen-implanted layer 506; the first silicon epitaxial layer 508 corresponds to the high thermal conductivity region 106 shown in FIG. 1A; the first silicon epitaxial layer 508 has a bottom portion 508a and the sidewall portion 508b; see Par.[0087]-[0089] wherein the second silicon epitaxial layer is epitaxially grown on the carbon-implanted layer; the second silicon epitaxial layer is epitaxially grown using CVD techniques (e.g., MOCVD, APCVD, LPCVD, UHVCVD), MBE, ALD, other suitable techniques, or combinations thereof; see Par.[0092]-[0101] wherein the second silicon epitaxial layer 512 shown in FIG. 5K is doped; the second silicon epitaxial layer 512 shown in FIG. 5K transforms to the collector region 108 shown in FIG. 5L; the fourth silicon epitaxial layer 516 is formed on the buffer region 110; the fourth silicon epitaxial layer 516 corresponds to the drift region 112 (a portion of it is used to form the body region 114, the source regions 116a and 116b) shown in FIG. 1A).
With respect to claim 7, Lin discloses, in Figs.1-8, the semiconductor device, wherein the epitaxial stopper layer contacts the inner side surface of the recessed region, extends upwardly along the inner side surface, has a first thickness on the inner side surface of the recessed region, and has a second thickness less than the first thickness on the bottom surface of the recessed region (see Fig.1D).
With respect to claim 8, Lin discloses, in Figs.1-8, the semiconductor device, wherein the epitaxial stopper layer includes a stopper layer (106) in the recessed region and a stopper protrusion/(vertical portion) on an upper surface of the stopper layer (see Fig.1D).
With respect to claim 9, Lin discloses, in Figs.1-8, the semiconductor device, wherein the epitaxial stopper layer is on the bottom surface of the recessed region, without extending along the inner side surface of the recessed region (see Fig.1D).
With respect to claim 12, Lin discloses, in Figs.1-8, the semiconductor device, wherein a thickness from a lower surface of the first semiconductor layer to the upper surface of the third semiconductor layer ranges from about 150 nm to about 700 nm (see Par.[0052] wherein the device depth (i.e., the distance between the bottom surface of the collector region 108 and the top surface 190 of the semiconductor substrate 102 in the Z-direction) ranges from 2 μm to 200 μm; the thickness (both in the Z-direction and the X-direction) of the collector region 108 ranges from 0.1 μm to 1 μm. In one example, the thickness (both in the Z-direction and the X-direction) of the buffer region 110 ranges from 0.05 μm to 1 μm; the thickness (both in the Z-direction and the X-direction) of the high thermal conductivity region 106 ranges from 0.1 μm to 300 μm. And the thickness of the high thermal conductivity region 106 in the Z-direction may be the same as or different from the thickness of the high thermal conductivity region 106 in the X-direction in different embodiments; the thickness of the isolation region 104b in the X-direction is larger than 0.1 μm).
With respect to claim 13, Lin discloses, in Figs.1-8, the semiconductor device, further comprising: a first source layer on the first protrusion, outside of the dummy gate structure, and having the first conductivity type; a second source layer on the second protrusion, outside of the dummy gate structure, and having the second conductivity type; and a third source layer on the third protrusion, outside of the dummy gate structure, and having the first conductivity type (see Par.[0131]-[0137] wherein the source regions 116a and 116b are connected (or alternatively being regarded as “one-piece”, collectively referred to as “the source region 116”) as shown in FIG. 6B; the source regions 116a and 116b are disposed in the body region 114; the source regions 116a and 116b are encircled by the body region 114 in the horizontal directions).
With respect to claim 14, Lin discloses, in Figs.1-8, the semiconductor device, further comprising contact plugs on the first to third source layers (see Fig.1D, wherein collector, gate and emitter contacts are shown).
With respect to claim 15, Lin discloses, in Figs.1-8, a semiconductor device comprising: a substrate (102) having a first region on which a recessed region (504) is disposed and a second region; a first semiconductor region (108) on a bottom surface and an inner side surface of the recessed region (504) and including first conductivity type/(P type) impurities; a second semiconductor region (110) on the first semiconductor region (108) in the recessed region (504) and including second conductivity type/(N type) impurities; a third semiconductor region (114) on the second semiconductor region (110) in the recessed region (504) and including the first conductivity type/(P type) impurities; and an epitaxial stopper layer (106) covering at least a portion of outer surfaces of the first semiconductor region (108) including a bottom surface, wherein each of the first to third semiconductor regions is formed of an epitaxial layer (see Par.[0074] wherein in the example shown in FIG. 5B, the trench 504 is formed by etching the semiconductor substrate 102; see Par.[0045]-[0047] wherein the collector region 108 is disposed on the high thermal conductivity region 106; the collector region 108 includes a bottom portion 108a and a sidewall portion 108b; the bottom portion 108a extends in the horizontal plane (i.e., the X-Y plane as shown in FIG. 1); the collector region 108 is p-type and heavily doped (i.e., p+); see Par.[0049]-[0054] wherein the buffer region 110 is disposed on the collector region 108; the buffer region 110 includes a bottom portion 110a and a sidewall portion 110b; the bottom portion 110a extends in the horizontal plane (i.e., the X-Y plane as shown in FIG. 1); the bottom portion 110a is disposed on the bottom portion 108a of the collector region 108; the buffer region 110 is of the second conductive type opposite to the first conductive type and heavily doped; see Par.[0033] wherein in FIGS. 1A-1C, the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112; see Par.[0041]-[0042] wherein the thermal conductivity of the high thermal conductivity region 106 is larger than 4 W/cm.Math.K; since the high thermal conductivity region 106 has a high thermal conductivity and a large contact area with the collector region 108 due to the non-planar structure of the high thermal conductivity region 106, the large amount of heat generated during the operation of the IGBT 100 can be dissipated or removed faster through the high thermal conductivity region 106; the high thermal conductivity region 106 is made of a silicon compound; the high thermal conductivity region 106 is made of silicon carbide (SiC); see Par.[0030] wherein the high thermal conductivity region is introduced using epitaxial growth of a silicon epitaxial layer, during which carbon is used as a material source as well; see Par.[0033] wherein in FIGS. 1A-1C, the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112, a body region 114, two source regions 116a and 116b, an emitter electrode 118, two gate dielectric structures 120a and 120b, two gate electrodes 122a and 122b, and two collector electrodes 124a and 124b; see Par.[0048] wherein a silicon epitaxial layer can be formed on the high thermal conductivity region 106 before the collector region 108 is formed thereon; the high thermal conductivity region 106 and the collector region 108 sandwich a silicon epitaxial layer; see Par.[0079]-[0080] wherein the first silicon epitaxial layer 508 is formed on the oxygen-implanted layer 506; the first silicon epitaxial layer 508 corresponds to the high thermal conductivity region 106 shown in FIG. 1A; the first silicon epitaxial layer 508 has a bottom portion 508a and the sidewall portion 508b; see Par.[0087]-[0089] wherein the second silicon epitaxial layer is epitaxially grown on the carbon-implanted layer; the second silicon epitaxial layer is epitaxially grown using CVD techniques (e.g., MOCVD, APCVD, LPCVD, UHVCVD), MBE, ALD, other suitable techniques, or combinations thereof; see Par.[0092]-[0101] wherein the second silicon epitaxial layer 512 shown in FIG. 5K is doped; the second silicon epitaxial layer 512 shown in FIG. 5K transforms to the collector region 108 shown in FIG. 5L; the fourth silicon epitaxial layer 516 is formed on the buffer region 110; the fourth silicon epitaxial layer 516 corresponds to the drift region 112 (a portion of it is used to form the body region 114, the source regions 116a and 116b) shown in FIG. 1A).
With respect to claim 16, Lin discloses, in Figs.1-8, the semiconductor device, wherein the epitaxial stopper layer (106) includes a material different from materials of the first to third semiconductor regions (see Par.[0033] wherein in FIGS. 1A-1C, the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112; see Par.[0041]-[0042] wherein the thermal conductivity of the high thermal conductivity region 106 is larger than 4 W/cm.Math.K; since the high thermal conductivity region 106 has a high thermal conductivity and a large contact area with the collector region 108 due to the non-planar structure of the high thermal conductivity region 106, the large amount of heat generated during the operation of the IGBT 100 can be dissipated or removed faster through the high thermal conductivity region 106; the high thermal conductivity region 106 is made of a silicon compound; the high thermal conductivity region 106 is made of silicon carbide (SiC)).
With respect to claim 17, Lin discloses, in Figs.1-8, the semiconductor device, further comprising interconnection lines (124) on the first to third semiconductor regions and a buried interconnection line on a level lower than a level of the epitaxial stopper layer (see Par.[0033] wherein the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112, a body region 114, two source regions 116a and 116b, an emitter electrode 118, two gate dielectric structures 120a and 120b, two gate electrodes 122a and 122b, and two collector electrodes 124a and 124b).
With respect to claim 19, Lin discloses, in Figs.1-8, a semiconductor device comprising: a substrate (102) having a recessed region (504) (see Par.[0074] wherein in the example shown in FIG. 5B, the trench 504 is formed by etching the semiconductor substrate 102); a first semiconductor region (108) on a bottom surface and an inner side surface of the recessed region (504) and including first conductivity type/(P type) impurities (see Par.[0045]-[0047] wherein the collector region 108 is disposed on the high thermal conductivity region 106; the collector region 108 includes a bottom portion 108a and a sidewall portion 108b; the bottom portion 108a extends in the horizontal plane (i.e., the X-Y plane as shown in FIG.1); a second semiconductor region (110) on the first semiconductor region in the recessed region and including second conductivity type impurities/(N type) (see Par.[0049]-[0054] wherein the buffer region 110 is disposed on the collector region 108; the buffer region 110 includes a bottom portion 110a and a sidewall portion 110b; the bottom portion 110a extends in the horizontal plane (i.e., the X-Y plane as shown in FIG. 1); a third semiconductor region (114) on the second semiconductor region in the recessed region and including the first conductivity type impurities/(N type) (see Par.[0054]-[0055] wherein the body region 114 is of the first conductive type and lightly doped. In the example shown in FIGS. 1A-1C, the body region 114 is p-type and lightly doped (i.e., p−); the body region 114 serves as the body of the first MOSFET and the drain of the second MOSFET); and an epitaxial stopper layer (106) covering at least a portion of outer surfaces of the first semiconductor region including a bottom surface, wherein the first to third semiconductor regions and the epitaxial stopper layer have a region entirely overlapping in a direction, perpendicular to an upper surface of the substrate (see Par.[0033] wherein in FIGS. 1A-1C, the IGBT 100 includes, among other components, a semiconductor substrate 102, an isolation region 104b, a high thermal conductivity region 106, a collector region 108, a buffer region 110, a drift region 112; see Par.[0041]-[0042] wherein the thermal conductivity of the high thermal conductivity region 106 is larger than 4 W/cm.Math.K; since the high thermal conductivity region 106 has a high thermal conductivity and a large contact area with the collector region 108 due to the non-planar structure of the high thermal conductivity region 106, the large amount of heat generated during the operation of the IGBT 100 can be dissipated or removed faster through the high thermal conductivity region 106; the high thermal conductivity region 106 is made of a silicon compound; the high thermal conductivity region 106 is made of silicon carbide (SiC); see Par.[0030] wherein the high thermal conductivity region is introduced using epitaxial growth of a silicon epitaxial layer, during which carbon is used as a material source as well).
With respect to claim 20, Lin discloses, in Figs.1-8, the semiconductor device, wherein the epitaxial stopper layer has a first thickness on the inner side surface of the recessed region, and has a second thickness less than the first thickness, on the bottom surface of the recessed region (see Fig.1D).
Allowable Subject Matter
Claims 10-11, 18 are objected to as being dependent upon a rejected base claims 1, 15, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818