DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Invention II (claim 9-20 and 1) and Applicant’ election with traverse of Species C in the reply filed on May 26th, 2026 is acknowledged.
The traversal is on the ground(s) that Species C of Figs. 9-11 belongs to a single semiconductor manufacturing process includes multiple steps in Fig. 1A-11. This is found persuasive and therefore, the restriction among Species A, B, C and D is withdrawn.
Claims 2-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 11 recites “a first frontside contact side”, “a second frontside contact size”, “a first backside contact size”, and “a second backside contact size”. It is unclear to the examiner how to measure or define the “size” because the claim fails to recite the “size” belongs to any structures of the device.
Claim 17 recites “replacing the backside sacrificial region with the backside contact” in line 3. It is unclear to the examiner how to replace the backside sacrificial region with the backside contact when “a backside contact” already formed on the first S/D region in line 3 of claim 10.
Claims 18-20 are rejected for being depended on claim 17 and having the above issue incorporated into the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9-10, and 12-15 and are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nam et al. (Pub. No.: US 2025/0120165 A1), hereinafter as Nam.
Regarding claim 1, Nam discloses a semiconductor device in Figs. 1-3 comprising: a first source or drain (S/D) region (left source/drain region SD) (see Fig. 3 and [0038]); a second S/D region (right source/drain region SD) (see Fig. 3 and [0038]); and an angled isolation pillar (insulation layer 132) between the first S/D region and the second S/D region (see Fig. 3 and [0049]).
Regarding claim 9, Nam discloses a method for forming a semiconductor device in Figs. 10-24 comprising: forming a first source or drain (S/D) region (left source/drain region SD) (see Fig. 10 and [0084-0088]); forming a second S/D region (right source/drain region SD) (see Fig. 10 and [0088]); and forming an angled isolation pillar (insulation layer 132) between the first S/D region and the second S/D region (see Fig. 10 and [0090]).
Regarding claim 10, Nam discloses the method of claim 9, further comprising: forming a frontside contact (contact CA2) on the second S/D region (see Figs. 13-19 and [0097-0113]); and forming a backside contact (power rail wiring 230) on the first S/D region (indirectly on left source/drain region SD) (see Figs. 20-24 and [0116-0125]).
Regarding claim 12, Nam discloses the method of claim 10, wherein the first S/D region is electrically coupled to a backside of the semiconductor device (the backside of IC device 10) through the backside contact device (through power rail wiring 230) and the second S/D region is electrically coupled to a frontside of the semiconductor device (defined by top surface of insulation layer 150 of IC device 10) through the frontside contact (contact CA and via structure 160) (see Fig. 24 and [0110-0114]).
Regarding claim 13, Nam discloses the method of claim 12, wherein the first S/D region is not electrically coupled to the frontside of the semiconductor device (right source/drain region SD is not electrically coupled to the top surface of insulation layer 150) and the second S/D region is not electrically coupled to the backside of the semiconductor device (left source/drain region SD is not electrically coupled to the bottom surface of insulating structure 220) (see Fig. 24 and [0109], [0120]).
Regarding claim 14, Nam discloses the method of claim 10, further comprising forming a nanosheet stack (nanosheet stack NS) comprising one or more nanosheets in direct contact with the first S/D region and the second S/D region (see Figs. 2, 4 and [0040]).
Regarding claim 15, Nam discloses the method of claim 10, wherein a width of the backside contact (width of power rail wiring 230) is greater than a width of the one or more nanosheets (width of nanosheet NS) (see Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (Pub. No.: US 2025/0120165 A1), hereinafter as Nam as applied to claim 10 above, and further in view of Sarkar et al. (Pub. No.: US 2025/0167118 A1), hereinafter as Sarkar.
Regarding claim 16, Nam discloses the method of claim 10, further comprising: forming a frontside interconnect (via structure 160) on the frontside contact (see Fig. 19 and [0113]), but fails to disclose further comprising: forming a backside interconnect on the backside contact.
Sarkar discloses a method comprising forming a backside contact (conductive 274) on a first S/D region (top S/D 222a) and forming a backside interconnect (BSPDN 280) on the backside contact (see Fig. 15A and [0034], [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the backside interconnect of the method of Sarkar into the method of Nam for connecting to the backside contact because the modified structure would provide a reliable and effective way for having a power line to bias the source/drain of the transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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