DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2016/0315028 to Chou (hereinafter Chou) in view of US PG Pub 2011/0286191 to Kim et al (hereinafter Kim).
Regarding Claim 1, Chou discloses a semiconductor package comprising:
a package substrate including a body layer (110, Fig. 1) having a central area and a peripheral area adjacent the central area, a first protective layer (124) on a top surface of the body layer, and a second protective layer (see below) on the first protective layer only in the peripheral area;
a semiconductor chip (140) mounted on the first protective layer in the central area in a flip- chip structure through first connection terminals (Fig 1);
an underfill (150) in a gap between the first protective layer and the semiconductor chip, and in a gap between the first connection terminals (Fig. 1);
an interposer (160) on the semiconductor chip opposite the package substrate; and
inter-substrate connection terminals (130) in the peripheral area of the package substrate and electrically connecting the package substrate to the interposer;
wherein the underfill has an anchor structure (128) extending into the first protective layer.
Chou does not disclose a second protective layer on the first protective layer only in the peripheral area.
Kim discloses a semiconductor package having a chip (Fig. 1, 130) with an underfill (140) on top of a first protective layer (128). A second protective layer (124) is on the first protective layer only in the peripheral area.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the structure of Chou such that it included a second protective layer on the first protective layer only in the peripheral region to provide for an underfill dam that ensures the underfill does not expand beyond the central region the chip is located.
Regarding Claim 2, the combination of Chou and Kim makes obvious the semiconductor package of Claim 1 wherein the anchor structure is positioned along a peripheral portion of the semiconductor chip (Fig. 1).
Regarding Claim 3, the combination of Chou and Kim makes obvious the semiconductor package of Claim 2 wherein the anchor structure comprises a plurality of anchors arranged at intervals along the peripheral portion of the semiconductor chip (Fig. 2D).
Regarding Claim 4, the combination of Chou and Kim makes obvious the semiconductor package of Claim 3 wherein each of the anchors has a shape of a cylinder, a polygonal column, a truncated pyramid, or an inverted pyramid (Fig. 2C).
Regarding Claim 5, the combination of Chou and Kim makes obvious the semiconductor package of Claim 2 wherein the semiconductor chip has a rectangular shape, and the anchor structure has a rectangular ring shape extending along the peripheral portion of the semiconductor chip (Fig. 2A).
Regarding Claim 6, the combination of Chou and Kim makes obvious the semiconductor package of Claim 5, wherein a cross section of the anchor structure, perpendicular to a direction in which the rectangular ring shape extends, has a shape of a rectangle, a trapezoid, or an inverted trapezoid (Fig. 2C).
Regarding Claim 7, the combination of Chou and Kim makes obvious the semiconductor package of Claim 1, wherein the anchor structure extends into an upper portion of the first protective layer, and a part of the first protective layer is between the anchor structure and the body layer (Fig. 1).
Regarding Clam 8, the combination of Chou and Kim makes obvious the semiconductor package of Claim 7 wherein the inter-substrate connection terminals extend through the second protective layer and the first protective layer and are electrically connected to terminal substrate pads on the body layer, and the first connection terminals extend through the first protective layer and are electrically connected to chip substrate pads on the body layer (Fig. 1).
Regarding Claim 9, the combination of Chou and Kim makes obvious the semiconductor package of Claim 8 wherein the first connection terminals respectively comprises a solder bump and a pillar, wherein the solder bumps extend through the first protective layer and are connected to the chip substrate pads and upper portions thereof protrude from the first protective layer, and the underfill extend on the upper portions of the solder bumps and on side surfaces of the pillars (Fig. 1).
Claims 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kim and US Patent No. 10,002,857 to Solimando et al (hereinafter Solimando).
Regarding Claim 11, Chou discloses a semiconductor package comprising:
a package substrate (110, Fig. 1) including a body layer having a central area and a peripheral area adjacent the central area, a first protective layer (126) on a top surface of the body layer, and a second protective layer (see below) on the first protective layer only in the peripheral area;
a semiconductor chip (140) mounted on the first protective layer in the central area in a flip- chip structure through first connection terminals (Fig. 1);
an underfill (150) in a gap between the first protective layer and the semiconductor chip, and in a gap between the first connection terminals, the underfill having an anchor structure (128) extending into the first protective layer;
an interposer (160) on the semiconductor chip and the sealer opposite the package substrate; and
inter-substrate connection terminals (130) in the peripheral area of the package substrate and extending through the sealer to electrically connect the package substrate to the interposer.
Chou does not disclose a second protective layer on the first protective layer only in the peripheral area.
Kim discloses a semiconductor package having a chip (Fig. 1, 130) with an underfill (140) on top of a first protective layer (128). A second protective layer (124) is on the first protective layer only in the peripheral area.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the structure of Chou such that it included a second protective layer on the first protective layer only in the peripheral region to provide for an underfill dam that ensures the underfill does not expand beyond the central region the chip is located.
Chou does not disclose a sealer sealing the semiconductor chip and the underfill.
Solimando discloses a semiconductor package which includes a sealer (216; Fig. 2) on the package substrate (212) and sealing a semiconductor chip (211) and an underfill (214).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the package of Chou to have included a sealer sealing the semiconductor chip and the underfill. Sealants would have provided obvious benefits such as isolation of the components within the package and/or a planarizing material upon which additional upper components, like an interposer, could have been placed on and even mechanically supported by the sealant.
Regarding Claim 12, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 11 wherein the anchor structure comprises a plurality of anchors arranged at intervals along a peripheral portion of the semiconductor chip (Fig. 2D).
Regarding Claim 13, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 11 wherein the semiconductor chip has a rectangular shape, and the anchor structure has a rectangular ring shape extending along a peripheral portion of the semiconductor chip (Fig. 2A).
Regarding Claim 14, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 11 wherein the anchor structure extends into an upper portion of the first protective layer, and a portion of the first protective layer is between the anchor structure and the body layer (Fig. 1).
Regarding Claim 15, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 14 wherein the inter-substrate connection terminals extend through the second protective layer and the first protective layer and are electrically connected to terminal substrate pads on the body layer, and the first connection terminals extend through the first protective layer and are electrically connected to chip substrate pads on the body layer (Fig. 1).
Regarding Claim 16, Chou discloses a semiconductor package in a package on package (POP) structure, the semiconductor package comprising:
a lower package (100, Fig.1); and
wherein the lower package comprises
a package substrate (110, Fig. 1) including a body layer having a central area and a peripheral area adjacent the central area, a first protective layer (126) on a top surface of the body layer, and a second protective layer (see below) on the first protective layer only in the peripheral area,
a first semiconductor chip (140) mounted on the first protective layer in the central area in a flip-chip structure through first connection terminals (124),
an underfill (150) in a gap between the first protective layer and the first semiconductor chip, and in a gap between the first connection terminals, the underfill having an anchor structure (128) extending into the first protective layer,
an interposer (160) on the first semiconductor chip opposite the package substrate, and inter-substrate connection terminals (130) on the peripheral area of the package substrate and electrically connecting the package substrate and the interposer.
Chou does not disclose a second protective layer on the first protective layer only in the peripheral area.
Kim discloses a semiconductor package having a chip (Fig. 1, 130) with an underfill (140) on top of a first protective layer (128). A second protective layer (124) is on the first protective layer only in the peripheral area.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the structure of Chou such that it included a second protective layer on the first protective layer only in the peripheral region to provide for an underfill dam that ensures the underfill does not expand beyond the central region the chip is located.
Chou does not disclose an upper package on the lower package.
Solimando makes obvious a semiconductor package having an upper package (containing chip 221) on a lower package (containing chip 211).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the package of Chou to have included an upper package over the lower package detailed by Chou. Numerous chips, dies and devices would have been conceivably attached to the interposer of Chou to form complex circuitry required for modern semiconductor devices.
Regarding Claim 17, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 16 wherein the first semiconductor chip has a rectangular shape, and wherein the anchor structure comprises a plurality of anchors arranged at intervals along a peripheral portion of the first semiconductor chip, or the anchor structure has a rectangular ring shape extending along the peripheral portion of the first semiconductor chip (Fig. 2A).
Regarding Claim 18, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 16 wherein the anchor structure extends into an upper portion of the first protective layer, and a part of the first protective layer is between the anchor structure and the body layer (Fig. 1).
Regarding Claim 19, the combination of Chou, Kim and Solimando makes obvious the semiconductor package of Claim 16, wherein the upper package is stacked on the lower package through inter-package connection terminals, and the upper package comprises at least one second semiconductor chip (Fig. 2; Solimando).
Regarding Claim 20, the combination of Chou. Kim and Solimando makes obvious the semiconductor package of Claim 19, wherein the first semiconductor chip comprises a logic chip, and the at least one second semiconductor chip comprises a memory chip (Solimando Col. 4 Lines 54-63 & Col. 5 Lines 15-29).
Regarding Claim 10, the combination of Chou and Kim makes obvious the semiconductor package of Claim 1 but does not disclose wherein the interposer comprises protrusions on a bottom surface of the interposers which are in contact with the semiconductor chip.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed the interposer to include protrusions on a bottom surface of an area corresponding to the central area which are in contact with a top surface of the semiconductor chip. Solimando notes the need for thermal interfaces between the chip and the interposer and utilizes a thermal material to compensate for the heat generated by the chip. Based on the teachings of the references of record, various embodiments, including protrusions as claimed by Applicant, would have been obvious examples of thermal interfaces between the chip and interposer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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