DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 13-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 05/11/2026. Tese groups are mutually exclusive and would require the examiner additional search. For example the distance limitation at the end of the claim 13 is not addressed in the first group, and claim 18 discusses about the liner having a concave region, which is not disclosed in the first group.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-9,12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US Pub No. 20200381564).
With respect to claim 1, Kang et al discloses an active pattern extending in a first direction (AP,Fig.3,D1); a plurality of gate structures (GE,Gox,Gs) spaced apart from each other in the first direction on the active pattern (Fig.3), each gate structure comprising a gate electrode extending in a second direction (GE) and a gate spacer on a sidewall of the gate electrode (GOX,GS); and a source/drain pattern (SD) disposed between adjacent gate structures and comprising a semiconductor liner layer (SP1) and a semiconductor filling layer (Sp2) on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are each formed of the same compound semiconductor material (Para 31), wherein the semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern (Fig.3), wherein the semiconductor liner layer comprises an outer surface in contact with the active pattern (outer SP1) and an inner surface facing the semiconductor filling layer (Fig.3), and in plan view, the inner surface of the semiconductor liner layer comprises a concave region (Fig.3,Fig.4A); furthermore, Kang et al discloses wherein a maximum width of the upper portion of the semiconductor filling layer (Sp2 on very top) in the first direction is greater than a width of the semiconductor filling layer in the first direction on the upper surface of the active pattern (right on the bottom, the claim does not require direct contact). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, regarding concave shape “In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.)”
With respect to claim 6, Kang et al discloses wherein the gate spacer comprises an inner wall (left side of GOX,Fig.4C) facing the gate electrode and extending in the second direction (Fig.4C), and a connection sidewall connected to the inner wall of the gate spacer (GS) and extending in the first direction (Fig.4C), the semiconductor liner layer is in contact with the connection sidewall of the gate spacer (Fig.4C), in plan view (Fig.4C), an inner surface of the semiconductor liner layer comprises a first point in contact with the connection sidewall of the gate spacer (top portion of Sp1,Fig.4c), a center point (where slope of inner Sp1 is zero), and a second point between the first point and the center point (any point between the two), the second point is spaced apart from the inner wall of the gate spacer by a first distance in the first direction (Fig.4C), the first point is spaced apart from the inner wall of the gate spacer in the first direction by a second distance (Fig.4C) different from the first distance (Fig.4C) , and the center point is spaced apart from the inner wall of the gate spacer in the first direction by a third distance different from the first distance (Fig.4C).
With respect to claim 7, the arts cited above do not explicitly disclose wherein the first distance is greater than the second distance and the third distance. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With respect to claim 8, the arts cited above do not explicitly disclose wherein the first distance is smaller than the second distance and the third distance. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With respect to claim 9, Kang discloses wherein the first distance is smaller than the second distance and greater than the third distance (when the second point is very close to the first point,Fig.4C).
With respect to claim 12, Kang discloses, wherein the active pattern comprises a lower pattern (AP) extending in the first direction and a plurality of sheet patterns spaced apart from the lower pattern in the third direction (CH), and the semiconductor liner layer is in contact with the lower pattern and the plurality of sheet patterns (Fig.3).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US Pub No. 20200381564), in view of Cheng et al (US Pub No. 20199237559).
With respect to claim 2, Kang et al does not explicitly disclose wherein the gate spacer comprises a first spacer and a second spacer, the first spacer is disposed between the gate electrode and the second spacer, the first spacer comprises an extension portion extending in the second direction along the sidewall of the gate electrode and a protrusion portion protruding from the extension portion of the first spacer in the first direction, and the upper portion of the semiconductor filling layer overlaps the protrusion portion of the first spacer in the third direction. On the other hand, Cheng et al discloses wherein the gate spacer comprises a first spacer (346,Fig.15) and a second spacer (350), the first spacer is disposed between the gate electrode (348) and the second spacer (Fig.15), the first spacer comprises an extension portion extending in the second direction along the sidewall of the gate electrode ( the portion of 346 directly touching 348, in the z direction, because these are 3 dimensional devices) and a protrusion portion (bottom portion of 346) protruding from the extension portion of the first spacer in the first direction (in the x direction), and the upper portion of the semiconductor filling layer overlaps the protrusion portion of the first spacer in the third direction (338 overlaps that portion in the y direction). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the Kang et al such that the top portion of the filling layer protrudes inside the sidewall spacer, in order to protect it from further processes.
With respect to claim 3, Cheng et al discloses wherein a part of the second spacer (t’s bottom portion) extends along an upper surface of the source/drain pattern (Fig.15).
With respect to claim 4, Kang et al discloses further comprising a source/drain etching stop layer (IL) disposed on the source/drain pattern and extending along a sidewall of the gate spacer (Fig.3), wherein the source/drain etching stop layer is in contact with the second spacer ( with contact with GS).
With respect to claim 5, Kang et al discloses wherein, in plan view (Fig.3), a part of the semiconductor liner layer (it’s top surface near the gate) protrudes beyond the first spacer in the first direction toward the semiconductor filling layer (Fig.3).
With respect to claim 10, Kang et al in Fig.3 does not explicitly disclose wherein the source/drain pattern further comprises a semiconductor insertion layer disposed between the semiconductor liner layer and the semiconductor filling layer, and the semiconductor liner layer, the semiconductor filling layer and the semiconductor insertion layer are each formed of silicon-germanium. On the other hand, Kang et al discloses in Fig.6A-B) discloses wherein the source/drain pattern further comprises a semiconductor insertion layer (Spa or spb) disposed between the semiconductor liner layer and the semiconductor filling layer (Fig.6A), and the semiconductor liner layer, the semiconductor filling layer and the semiconductor insertion layer are each formed of silicon-germanium (Para 31-48). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Fig.3 according to the teachings of the Fig.6A, such that a semiconductor insertion layer disposed between the semiconductor liner layer and the semiconductor filling layer, and the semiconductor liner layer, the semiconductor filling layer and the semiconductor insertion layer are each formed of silicon-germanium as a design choice.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US Pub No. 20200381564), in view of Kim et al (US Pub No.20150214051).
With respect to claim 11, the arts cited above do not explicitly disclose wherein the source/drain pattern further comprises a semiconductor capping layer disposed on the semiconductor filling layer, the semiconductor capping layer is in contact with the semiconductor filling layer and is not in contact with the semiconductor liner layer, the semiconductor liner layer, the semiconductor filling layer and the semiconductor capping layer are each formed of silicon-germanium, and a germanium fraction of the semiconductor capping layer is smaller than a germanium fraction of the semiconductor filling layer. On the other hand, Kim et al discloses wherein the source/drain pattern further comprises a semiconductor capping layer (240,250,Fig.25) disposed on the semiconductor filling layer (205,210,225) the semiconductor capping layer is in contact with the semiconductor filling layer and is not in contact with the semiconductor liner layer (190), the semiconductor liner layer, the semiconductor filling layer and the semiconductor capping layer are each formed of silicon-germanium (para 55-100). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to of ordinary skill in the art to form a capping layer on the filing layer, in order to make a contact region for the source and the drain region. However, the arts cited above do not explicitly disclose and a germanium fraction of the semiconductor capping layer is smaller than a germanium fraction of the semiconductor filling layer. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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