DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of Invention I (semiconductor device), reflected in claims 1-15 in the reply filed on 12/07/2023 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 20230354570 A1, hereinafter Hwang’570) in view of Xie et al. (US 20230369219 A1, hereinafter Xie’219).
Regarding independent claim 1, Hwang’570 teaches, “A semiconductor device, (fig. 1-12; ¶ [0001] - ¶ [0076]) comprising:
a first transistor (first lower transistor, fig. 4A; ¶ [0025]) comprising a first source/drain (S/D) region (LSD1, ¶ [0025]);
a second transistor (first upper transistor, ¶ [0023]) stacked over the first transistor and comprising a second S/D region (USD1, ¶ [0023]);
a first backside power rail (BPR) (PR1) ((disposed below the first transistor));
a second BPR (PR2) ((disposed below the first BPR));
a via (PC1) by which the second S/D region (USD1) and the first BPR (PR1) are connected; and
metallization (PC2, a metallic material being implicit for such a contact), which ((passes through and)) is insulated from the first BPR (PC1), and by which the first S/D region (LSD1) and the second BPR (PR2) are connected”.
But Hwang’570 is silent upon the provision of wherein
the first backside power rail (BPR) disposed below the first transistor;
the second BPR disposed below the first BPR;
metallization, which passes through .. the first BPR,
However, Xie’219 teaches in ¶ [0033] that power planes provide a lower resistance when compared to metal levels of wires and vias that are typically used in power delivery networks. Referring to fig. 8 where the first power plane 208 is formed, but the same evidently also applies to the second power plane 210 shown in fig. 11. Xie’219 also discloses in fig. 11, a metallisation 262 passing through the upper power plane in order to connect the lower power plane 210 (here at Vss voltage, ¶ [0037]) to a source/drain region 232b. Applying this backside power plane concept to Hwang’570 results in:
- a first power rail also disposed below the first transistor (since the power rails
are power planes extending over the entire area in Xie’219, fig. 11),
- a second BPR disposed below the first BPR (see Xie’219, fig. 11), and
- a metallisation (corresponding to item 262 in Xie’219, fig. 11) connecting the first
(lower) S/D region to the second power rail (Vss is on the lower power rail in Xie’219,
see ¶ [0037]) that passes through the first power rail (see Xie’219, fig. 11).
Hwang’570 and Xie’219are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hwang’570 with the features of Xie’219because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Hwang’570 and Xie’219 to stack the two power planes vertically one above another according to the teachings of Xie’219 with a motivation of reducing ohmic resistance during the power transfer. See Xie’219, ¶ [0033].
Regarding claim 2, Hwang’570 modified with Xie’219 further teaches, “The semiconductor device according to claim 1, wherein the first and second transistors form a first stacked field effect transistor (SFET) (fig. 4A, Hwang’570)”.
Regarding claim 3, Hwang’570 modified with Xie’219 further teaches, “The semiconductor device according to claim 2, further comprising a second SFET comprising:
an additional first transistor comprising an additional first S/D region (LSD3, fig. 4A, Hwang’570);
an additional second transistor stacked over the additional first transistor and comprising an additional second S/D region (USD3); and
additional metallization (PC3), which passes through (see Xie’219, fig. 11 and explanation in the rejection of claim 1 above) and is insulated from the first BPR, and by which the additional first S/D region and the second BPR (VSS/PR2, PR3) are connected,
wherein the semiconductor device further comprises dielectric spacers (260, fig. 11, Xie’219) disposed along the metallization and the additional metallization to insulate the metallization and the additional metallization from the first BPR”.
Regarding claim 4 and 11, Hwang’570 modified with Xie’219 further teaches, “wherein the first and second BPRs are two-dimensional (2D) plates or planar features (figs. 8, 11, Xie’219)”.
Regarding claim 5 and 12, Hwang’570 modified with Xie’219 further teaches, “a frontside contact (SDC, fig. 4A, Hwang’570) by which the via (PC1) is connected to the second S/D region (USD1); and a backside contact (262, fig. 11, Xie’219) by which the metallization is connected to the first S/D region (LSD1, fig. 4A, Hwang’570)”.
Regarding independent claim 9, Hwang’570 teaches, “A semiconductor device, (fig. 1-12; ¶ [0001] - ¶ [0076]) comprising:
multiple stacked field effect transistors (SFETs) (respectively with source/drain regions LSD1/USD1 and LSD3/USD3)), each comprising:
a bottom FET (first lower transistor, fig. 4A; ¶ [0025]) comprising a bottom source/drain (S/D) region (LSD1, ¶ [0025]); and
a top FET (first upper transistor, ¶ [0023]) stacked over the bottom FET and comprising a top S/D region (USD1, ¶ [0023]);
a first backside power rail (BPR) (PR1) disposed below the bottom FET of each of the multiple SFETs;
a second BPR (PR2) disposed below the first BPR;
a via (PC1) by which the top S/D region (USD1) of one of the multiple SFETs and the first BPR (PR1) are connected; and
metallization (PC2, a metallic material being implicit for such a contact), which passes through and is insulated from the first BPR (PR1),
and by which the bottom S/D region (LSD1) of the one of the multiple SFETs and the second BPR (PR2) are connected”.
But Hwang’570 is silent upon the provision of wherein
the first backside power rail (BPR) disposed below the bottom FET of each of the multiple SFETs;
the second BPR disposed below the first BPR;
metallization, which passes through .. the first BPR,
However, Xie’219 teaches in ¶ [0033] that power planes provide a lower resistance when compared to metal levels of wires and vias that are typically used in power delivery networks. Referring to fig. 8 where the first power plane 208 is formed, but the same evidently also applies to the second power plane 210 shown in fig. 11. Xie’219 also discloses in fig. 11, a metallisation 262 passing through the upper power plane in order to connect the lower power plane 210 (here at Vss voltage, ¶ [0037]) to a source/drain region 232b. Applying this backside power plane concept to Hwang’570 results in:
- a first power rail also disposed below the first transistor (since the power rails
are power planes extending over the entire area in Xie’219, fig. 11),
- a second BPR disposed below the first BPR (see Xie’219, fig. 11), and
- a metallisation (corresponding to item 262 in Xie’219, fig. 11) connecting the first
(lower) S/D region to the second power rail (Vss is on the lower power rail in Xie’219,
see ¶ [0037]) that passes through the first power rail (see Xie’219, fig. 11).
Hwang’570 and Xie’219 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hwang’570 with the features of Xie’219 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Hwang’570 and Xie’219 to stack the two power planes vertically one above another according to the teachings of Xie’219 with a motivation of reducing ohmic resistance during the power transfer. See Xie’219, ¶ [0033].
Regarding claim 10, Hwang’570 modified with Xie’219 further teaches, “The semiconductor device according to claim 9, further comprising: additional metallization (PC3, fig. 4A, Hwang’570), which passes through (see Xie’219, fig. 11 and explanation in the rejection of claim 9 above) and is insulated from the first BPR, and by which the bottom S/D region of a second one of the multiple SFETs and the second BPR are connected; and dielectric spacers (260, fig. 11, Xie’219) disposed along the metallization and the additional metallization to insulate the metallization and the additional metallization from the first BPR”.
Claims 1, 6-9 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20230369218 A1, hereinafter Li’218) in view of Xie’219.
Regarding independent claim 1, Li’218 teaches, “A semiconductor device (figs. 1-9; ¶ [0001] - ¶ [0059]), comprising:
a first transistor comprising a first source/drain (S/D) region (118b);
a second transistor stacked over the first transistor and comprising a second S/D region (122b);
a first backside power rail (BPR) (184b) ((disposed below the first transistor));
a second BPR (184a) ((disposed below the first BPR));
a via (112b) by which the second S/D region (122b) and the first BPR (184b) are connected; and
metallization (170a), ((which passes through and)) is insulated from the first BPR (184b), and by which the first S/D region (118b) and the second BPR (184a) are connected”.
But Li’218 is silent upon the provision of wherein
the first backside power rail (BPR) disposed below the first transistor;
the second BPR disposed below the first BPR;
metallization, which passes through .. the first BPR,
However, Xie’219 teaches in ¶ [0033] that power planes provide a lower resistance when compared to metal levels of wires and vias that are typically used in power delivery networks. Referring to fig. 8 where the first power plane 208 is formed, but the same evidently also applies to the second power plane 210 shown in fig. 11. Xie’219 also discloses in fig. 11, a metallisation 262 passing through the upper power plane in order to connect the lower power plane 210 (here at Vss voltage, ¶ [0037]) to a source/drain region 232b. Applying this backside power plane concept to Hwang’570 results in:
- a first power rail also disposed below the first transistor (since the power rails
are power planes extending over the entire area in Xie’219, fig. 11),
- a second BPR disposed below the first BPR (see Xie’219, fig. 11), and
- a metallisation (corresponding to item 262 in Xie’219, fig. 11) connecting the first
(lower) S/D region to the second power rail (Vss is on the lower power rail in Xie’219,
see ¶ [0037]) that passes through the first power rail (see Xie’219, fig. 11).
Li’218 and Xie’219 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li’218 with the features of Xie’219 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Li’218 and Xie’219 to stack the two power planes vertically one above another according to the teachings of Xie’219 with a motivation of reducing ohmic resistance during the power transfer. See Xie’219, ¶ [0033].
Regarding independent claim 9, Li’218 teaches, “A semiconductor device (figs. 1-9; ¶ [0001] - ¶ [0059]), comprising:
multiple stacked field effect transistors (SFETs) (fig. 9c, two SFETs comprising source/drain regions 118b/122b and 118c/122c)), each comprising:
a bottom FET comprising a bottom source/drain (S/D) region (118b); and
a top FET stacked over the bottom FET and comprising a top S/D region (122b);
a first backside power rail (BPR) (184b) ((disposed below the bottom FET of each of the multiple SFETs));
a second BPR (184a) ((disposed below the first BPR));
a via (112b) by which the top S/D region (122b) of one of the multiple SFETs and the first BPR (184b) are connected; and
metallization (170a), which ((passes through and)) is insulated from the first BPR (184b),
and by which the bottom S/D region (118b) of the one of the multiple SFETs and the second BPR (184a) are connected”.
But Li’218 is silent upon the provision of wherein
the first backside power rail (BPR) disposed below the bottom FET of each of the multiple SFETs;
the second BPR disposed below the first BPR;
metallization, which passes through .. the first BPR,
However, Xie’219 teaches in ¶ [0033] that power planes provide a lower resistance when compared to metal levels of wires and vias that are typically used in power delivery networks. Referring to fig. 8 where the first power plane 208 is formed, but the same evidently also applies to the second power plane 210 shown in fig. 11. Xie’219 also discloses in fig. 11, a metallisation 262 passing through the upper power plane in order to connect the lower power plane 210 (here at Vss voltage, ¶ [0037]) to a source/drain region 232b. Applying this backside power plane concept to Hwang’570 results in:
- a first power rail also disposed below the first transistor (since the power rails
are power planes extending over the entire area in Xie’219, fig. 11),
- a second BPR disposed below the first BPR (see Xie’219, fig. 11), and
- a metallisation (corresponding to item 262 in Xie’219, fig. 11) connecting the first
(lower) S/D region to the second power rail (Vss is on the lower power rail in Xie’219,
see ¶ [0037]) that passes through the first power rail (see Xie’219, fig. 11).
Li’218 and Xie’219 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li’218 with the features of Xie’219 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Li’218 and Xie’219 to stack the two power planes vertically one above another according to the teachings of Xie’219 with a motivation of reducing ohmic resistance during the power transfer. See Xie’219, ¶ [0033].
Regarding claim 6, Li’218 modified with Xie’219 further teaches, “The semiconductor device according to claim 5, further comprising: another backside contact (170C, fig. 9C, Li’218); and a dielectric cap (182) self-aligned to and configured to insulate the another backside contact (170c) from the first BPR (184b)”.
Regarding claim 7 and 14, Li’218 modified with Xie’219 further teaches, “The semiconductor device according to claim 6, further comprising an etch stop layer (136, fig. 9C, Li’218) disposed to delimit a height of a portion of an upper surface of the another backside contact (170C)”.
Regarding claim 8, Li’218 modified with Xie’219 further teaches, “The semiconductor device according to claim 1, further comprising: a carrier wafer (164, fig. 9C, Li’218); a back-end-of-line (BEOL) layer (106b) interposed between the carrier wafer and the second transistor; and a plurality of additional frontside vias (154) by which other first and second S/D regions are connected to the BEOL layer (106b)”.
Regarding claim 13, Li’218 modified with Xie’219 further teaches, “The semiconductor device according to claim 12, further comprising: another backside contact (170C, fig. 9C, Li’218) of another one of the multiple SFETs; and a dielectric cap (182) to insulate the another backside contact from the first BPR (184b)”.
Regarding claim 15, Li’218 modified with Xie’219 further teaches, “The semiconductor device according to claim 9, further comprising: a carrier wafer (164, fig. 9C, Li’218); a back-end-of-line (BEOL) layer (106b) interposed between the carrier wafer and the top FET of each of the multiple SFETs; and a plurality of additional frontside vias (154) by which top and bottom S/D regions of other ones of the multiple stack FETs are connected to the BEOL layer (106b)”.
Conclusion
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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