DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/5/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 10-12, 15-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo (US 2020/0105770; hereinafter Yoo).
Regarding claim 1, Figs 1-2 of Yoo discloses an electronic device comprising:
a conductive material layer (Channel region in substrate; Fig 3; ¶ [0028]);
a ferroelectric layer (125; Fig 1; ¶ [0032]) covering the conductive material layer, the ferroelectric layer including a compound represented by HfxAyOz, where 0≤ x ≤ 1, 0≤ y ≤ 1 and 2(x+y)˂ z (¶ [0032]); and
an electrode layer (135; Fig 1; ¶ [0028]) covering the ferroelectric layer (125; Fig 1; ¶ [0032]).
Regarding claim 2, Figs 1-2 of Yoo discloses in the compound represented by HfxAyOz, A comprises at least one of Al, Si, Zr, Y, La, Gd, Sr, and Mg (¶ [0032]).
Regarding claim 3, Figs 1-2 of Yoo discloses A is Zr so the compound represented by HfxAyOz is a compound represented by HfxZryO2+a, where 2(x+y) < 2+a and 0 <a <1 (¶ [0023], [0032]).
Regarding claim 7, Figs 1-2 of Yoo discloses a thickness of the ferroelectric layer (125; Fig 1; ¶ [0032]) is 5nm (¶ [0026]) which anticipates the claimed range.
Regarding claim 10, Figs 1-2 of Yoo discloses a dielectric layer (115; Fig 2; ¶ [0031]) wherein the dielectric layer (115; Fig 2; ¶ [0031]) is between the conductive material layer (Channel region in substrate; Fig 3; ¶ [0028]) and the ferroelectric layer (125; Fig 1; ¶ [0032]).
Regarding claim 11, Figs 1-2 of Yoo discloses the conductive material layer (Channel region in substrate; Fig 3; ¶ [0028]) comprises a channel (¶ [0028]), and the electrode layer (135; Fig 1; ¶ [0028]) comprises a gate electrode (¶ [0028]).
Regarding claim 12, Figs 1-2 of Yoo discloses a substrate (101; Fig 1; ¶ [0028]) wherein the channel (Channel region in substrate; Fig 3; ¶ [0028]) is spaced apart from an upper surface of the substrate and the channel extends in a first direction (Fig 2).
Regarding claim 15, Figs 1-2 of Yoo discloses a semiconductor device comprising:
a conductive material layer (Channel region in substrate; Fig 3; ¶ [0028]) forming a channel;
a ferroelectric layer (125; Fig 1; ¶ [0032]) covering the conductive material layer;
a gate electrode layer (135; Fig 1; ¶ [0028]) covering the ferroelectric layer (125; Fig 1; ¶ [0032]);
a source region (102; Fig 2; ¶ [0028]) and a drain region (103; Fig 2; ¶ [0028]) electrically connected to both ends of the channel,
wherein the ferroelectric layer including a compound represented by HfxAyOz, where 0≤ x ≤ 1, 0≤ y ≤ 1 and 2(x+y)˂ z (¶ [0032]).
Regarding claim 16, Figs 4-8 of Yoo discloses a method of manufacturing a ferroelectric thin film, the method comprising:
forming a material layer (1251; Fig 6; ¶ [0067]) comprising Hf, A, and O on a base layer, and
crystallizing the material layer by performing heat treatment on the material layer in a vacuum environment to provide a crystallized ferroelectric layer (¶ [0070]), the crystallized ferroelectric layer comprising a compound represented by HfxAyOz, where 0≤ x ≤ 1, 0≤ y ≤ 1 and 2(x+y)˂ z (¶ [0067], [0070]).
Regarding claim 17, Figs 4-8 of Yoo discloses forming an electrode layer (130; Fig 8; ¶ [0071]) on the ferroelectric layer, wherein the heat treatment is performed after forming the electrode layer. (¶ [0071])
Regarding claim 20, Figs 4-8 of Yoo discloses the heat treatment is performed in a chamber in which the material layer is formed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 2020/0105770; hereinafter Yoo) in view of Yoo (US 2019/0244973; hereinafter Yoo_1).
Regarding claim 4, Figs 1-2 of Yoo discloses the ferroelectric layer (125; Fig 1; ¶ [0032]) comprises carbon (¶ [0033]).
However Yoo does not expressly disclose a content of the carbon is less than 33 at% with respect to an amount of Hf in the ferroelectric layer.
In the same field of endeavor, Yoo_1 discloses a ferroelectric layer can have a dopant such as carbon and concentration of the dopant can be 4 -6% (¶ [0114]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that concentration of the dopant in the ferroelectric layer is within the claimed range for the purpose of forming the ferroelectric layer with uniform distribution of dopant that helps in stabilizing the ferroelectricity of the ferroelectric layer (¶ [0035]).
Regarding claim 5, Figs 1-2 of Yoo discloses the ferroelectric layer (125; Fig 1; ¶ [0032]) comprises carbon (¶ [0033]).
However Yoo does not expressly disclose a content of the carbon is less than 10 at% with respect to an amount of Hf in the ferroelectric layer.
In the same field of endeavor, Yoo_1 discloses a ferroelectric layer can have a dopant such as carbon and concentration of the dopant can be 4 -6% (¶ [0114]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that concentration of the dopant in the ferroelectric layer is within the claimed range for the purpose of forming the ferroelectric layer with uniform distribution of dopant that helps in stabilizing the ferroelectricity of the ferroelectric layer (¶ [0035]).
Regarding claim 6, Figs 1-2 of Yoo discloses the ferroelectric layer (125; Fig 1; ¶ [0032]) comprises carbon (¶ [0033]).
However Yoo does not expressly disclose a content of the carbon is less than 6 at% with respect to an amount of Hf, A and O in the ferroelectric layer.
In the same field of endeavor, Yoo_1 discloses a ferroelectric layer can have a dopant such as carbon and concentration of the dopant can be 4 -6% (¶ [0114]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that concentration of the dopant in the ferroelectric layer is within the claimed range for the purpose of forming the ferroelectric layer with uniform distribution of dopant that helps in stabilizing the ferroelectricity of the ferroelectric layer (¶ [0035])
Claim(s) 8 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 2020/0105770; hereinafter Yoo).
Regarding claim 8, Yoo does not expressly disclose the ferroelectric layer is formed such that 2Pr is 10 µC/cm2 or greater.
However, the ordinary artisan would have recognized the material and the type of dopants used for the ferroelectric layer to be a result effective variable affecting the electrical characteristics such as Pr. Thus, it would have been obvious to vary the concentrations of materials and dopants in order to achieve the 2Pr within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 18, Figs 4-8 of Yoo discloses the heat treatment is performed at 350 °C (¶ [0062]).
However Yoo does not expressly disclose the heat treatment is performed in a vacuum environment with a pressure ranging from 1 E-7 Torr to 9E-4 Torr.
However, the ordinary artisan would have recognized pressure to be a result effective variable affecting the crystallization of the ferroelectric material. Thus, it would have been obvious to vary the pressure within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 19, Figs 4-8 of Yoo discloses the heat treatment is performed at a temperature of 350 °C (¶ [0062]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 2020/0105770; hereinafter Yoo) in view of Heo et al (US 2021/0305399; hereinafter Heo).
Regarding claim 9, Yoo does not expressly disclose the ferroelectric layer has a dielectric constant in a range of 15 to 25.
In the same field of endeavor, Heo discloses a ferroelectric layer (130; Fig 1; ¶ [0078]) comprising HfZrO having a dielectric constant greater than about 20 (¶ [0078]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a ferroelectric layer comprising HfZrO having a dielectric constant within the claimed range for the purpose of using known materials well known in the art for ferroelectric materials in order to achieve desired dielectric constant (¶ [0078]).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 2020/0105770; hereinafter Yoo) in view of Song et al (US 2020/0365733; hereinafter Song).
Regarding claim 13, Yoo does not expressly disclose the ferroelectric layer comprises a plurality of ferroelectric layers surrounding the plurality of channel elements, respectively and
the gate electrode protrudes from the upper surface of the substrate and surrounds the plurality of ferroelectric layers.
In the same field of endeavor, Figs 2 and 5 of Song discloses a ferroelectric layer (35; Fig 2; ¶ [0034]) comprises a plurality of ferroelectric layers (¶ [0034]) surrounding the plurality of channel elements (15; Fig 2) and a gate electrode (GS1; Fig 2; ¶ [0032]) protrudes from the upper surface of a substate (10; Fig 2) and surrounds the plurality of ferroelectric layers (Fig 2).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the ferroelectric layer comprises a plurality of ferroelectric layers surrounding the plurality of channel elements, respectively and the gate electrode protrudes from the upper surface of the substrate and surrounds the plurality of ferroelectric layers in order to form the fin type device (¶ [0030]).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 2020/0105770; hereinafter Yoo) in view of Song et al (US 2024/0130136; hereinafter Song_1).
Regarding claim 14, Yoo does not expressly disclose wherein the gate electrode is one of a plurality of gate electrodes in a stack structure, the stack structure includes the plurality of gate electrodes alternatively stacked with a plurality of insulating layers in a vertical direction, the stack structure includes a plurality of channel holes penetrating the stack structure in the vertical direction, and the ferroelectric layer and the conductive material layer are concentrically arranged inside the plurality of channel holes to form a memory cell string in which a plurality of memory cell strings are two-dimensionally arranged.
In the same field of endeavor, Figs 3 -7 of Song_1 discloses a gate electrode (UL/WL/LL; Fig 5) is one of a plurality of gate electrodes in a stack structure, the stack structure includes the plurality of gate electrodes alternatively stacked with a plurality of insulating layers (ILD; ¶ [0035]), the stack structure includes a plurality of channel hoels (CH; ¶ [0071]) penetrating the stack structure and the ferroelectric layer (FEL; ¶ [0072]) and conductive material are concentrically arranged to form a memory cell string.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the structure is arranged as claimed in order to form a semiconductor memory device which consumes lower power and provides a higher data rate (¶ [0004]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hsu et al (US 2020/0105897)
Lai et al (US 9978868)
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817