DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (Ma) (CN 110021617) as evidenced by or in view of Stacey (US 2005/0152422 A1) or Liu et al. (Liu) (US 2024/0213395 A1).
In regards to claim 1, Ma (Figs.1-3 and associated text and items) discloses a manufacturing method for a light sensing element (Figs. 1, 3), comprising the following steps: providing an epitaxy (item Si); performing a device process to form a semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown) on the epitaxy (item Si), wherein the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown) comprises a light absorbing layer (InGaAS layer) and a plurality of sidewalls; performing a wet etching process to form a recess (recesses shown) inward from a sidewall surface of each of the sidewalls (see Crosstalk restraining structure and/or beneficial effects section) of the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown); and performing a coating process to form a bandpass filter layer (SiN.sub.x layer) on the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown); wherein light incident from each of the sidewalls (sidewalls of InP, InAlAs, InAlGaAs, InGaAS structure shown) is blocked from entering the light absorbing layer (InGaAS layer) by the recess (recesses shown) of each of the sidewalls (sidewalls of InP, InAlAs, InAlGaAs, InGaAS structure shown).
As evidenced by Stacey (paragraph 44, Figs. 2-5) an epitaxy (item 12) can be an InP substrate. Also as evidenced by Liu (paragraph 36 Fig. 3) an epitaxy (item 11) can be an InP substrate.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Stacey and/or Liu for the purpose of stabilizing optical wavelength of optical radiation against temperature induced changes and/or sensing accuracy and reduced noise, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 2, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein the recess (recess/recesses shown) includes an inclined surface, the inclined surface forms an inclination angle with a top surface of the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown), and the inclination angle is not greater than 60 degrees (greater than 30 and less than 90 degrees, see crosstalk restraining structure section).
In regards to claim 3, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein the step of performing the device process to form the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown) on the epitaxy (item Si) further comprises the following steps: forming a first semiconductor layer (InAlAs or InAlGaAs layer) on the epitaxy (item Si); forming the light absorbing layer (InGaAS layer) on the first semiconductor layer (InAlAs or InAlGaAs layer); and forming a second semiconductor layer (InP, InAlAs or InP plus InAlAs layer) on the light absorbing layer (InGaAS layer) to constitute the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown) having the sidewalls by the first semiconductor layer (InAlAs or InAlGaAs layer), the light absorbing layer (InGaAS layer) and the second semiconductor layer (InP, InAlAs or InP plus InAlAs layer).
In regards to claim 4, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein the recess (recess shown) is at least between the top surface and the first semiconductor layer (InAlAs or InAlGaAs layer).
In regards to claim 5, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein a recessed depth of the recess relative to the sidewall surface increases as the recess approaches the light absorbing layer (InGaAS layer).
In regards to claim 6, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein the light absorbing layer (InGaAS layer) is made of indium gallium arsenide, and the second semiconductor layer (InP, InAlAs or InP plus InAlAs layer) is made of indium phosphide.
In regards to claim 7, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses H3PO4: H2O2: H2O=1: 3:6 (volume ratio) chemical solution (Ma), but does not specifically disclose wherein in the wet etching process, an etching solution containing hydrogen chloride, acetic acid and water or an etching solution containing rust water, rust substance and acetic acid is used to form the recess on each of the sidewalls.
It would have been obvious to modify the invention to include an etching solution containing hydrogen chloride, acetic acid and water or an etching solution containing rust water, rust substance and acetic acid, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 7, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein in the wet etching process, photoresist is first used to pre-process each of the sidewalls of the semiconductor structure, then an object on which the epitaxy and the semiconductor structure have been formed is laid flat in an etching tank with the etching solution, and the etching tank is agitated in isotropic concentric circles so that the semiconductor structure is etched by the etching solution to form the recess.
In regards to claim 9, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses wherein an area of the bandpass filter layer (SiN.sub.x layer) is larger than an area of the light absorbing layer (InGaAS layer).
In regards to claim 10, Ma (Figs.1-3 and associated text and items) as modified by Stacey and/or Liu discloses a light sensing element manufactured by the manufacturing method of claim 1, the light sensing element (Figs. 1, 3) at least comprising: an epitaxy (item Si, Ma, InP, Stacey/Liu); a semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown) located on the epitaxy (item Si, Ma, InP, Stacey/Liu), the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown) comprising a light absorbing layer (InGaAS layer) and a plurality of sidewalls (sidewalls shown), wherein each of the sidewalls (sidewalls shown) forms a recess (recess(es) shown) inward from a sidewall surface (sidewall surface shown), and light incident from each of the sidewalls (sidewalls shown) is blocked from entering the light absorbing layer (InGaAS layer) by the recess of each of the sidewalls (sidewalls shown); and a bandpass filter layer (SiN.sub.x layer) stacked on the semiconductor structure (InP, InAlAs, InAlGaAs, InGaAS structure shown).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 9, 2026