Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-10 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the semiconductor device" in line 1. There is insufficient antecedent basis for this limitation in the claim. Claims 7-10 are indefinite because of their dependence from claim 6.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (US Patent No. 6,297,162 B1), hereafter referred to as Jang.
As to claim 1, Jang discloses a semiconductor device (fig 15 including semiconductor substrate 100) comprising:
a first insulating film (fig 15, silicon dioxide layer 104);
a second insulating film (silicon oxynitride 116) provided on the first insulating film (104);
a third insulating film (silicon dioxide layer 124) provided on the second insulating film (116);
a first wiring (108) provided in a first groove provided in the first insulating film (groove filled with 108 in first insulating film 104); and
a second wiring (136) provided in a second groove provided in communication with the first insulating film (104), the second insulating film (116), and the third insulating film (124) and connected to the first wiring (108),
wherein the second insulating film contains silicon oxynitride (silicon oxynitride layer 116; col. 5, lines 41-53), the second insulating film has a processing selectivity higher than processing selectivity of the first insulating film and the third insulating film (col. 5, lines 41-53 teaches that layer 116 is used as an etch stop layer and silicon oxynitride has higher selectivity than silicon dioxide), and the second insulating film has a dielectric strength voltage higher than a dielectric strength voltage of silicon nitride (layer 116 is silicon oxynitride which has a higher dielectric strength voltage compared to silicon nitride as taught in [0040] of the application as well as fig 4 of Shi et al. provided in the notice of references cited).
As to claim 6, Jang discloses a method of manufacturing the semiconductor device (figs 9-15, semiconductor substrate 100) comprising:
forming a first insulating film (fig 9, 104);
forming a first groove in the first insulating film by selectively etching the first insulating film (fig 9, groove filled with wiring 108 taught in col. 5, lines 16-30);
forming a first wiring provided in the first groove (fig 9, wiring 108; col. 5, lines 16-30);
forming a second insulating film (116) provided on the first insulating film (104);
forming a third insulating film (124) provided on the second insulating film (116);
forming a second groove (fig 14, groove through 124, 116) provided in communication with the first insulating film (104), the second insulating film (116), and the third insulating film (124) and connected to the first wiring (108), by selectively etching the first insulating film, the second insulating film, and the third insulating film (col. 6, lines 30-40); and
forming a second wiring provided in the second groove (fig 15, wiring 136 in the groove),
wherein the second insulating film contains silicon oxynitride (silicon oxynitride layer 116; col. 5, lines 41-53), the second insulating film has a processing selectivity higher than processing selectivity of the first insulating film and the third insulating film (col. 5, lines 41-53 teaches that layer 116 is used as an etch stop layer and silicon oxynitride has higher selectivity than silicon dioxide), and the second insulating film has a dielectric strength voltage higher than a dielectric strength voltage of silicon nitride (layer 116 is silicon oxynitride which has a higher dielectric strength voltage compared to silicon nitride as taught in [0040] of the application as well as fig 4 of Shi et al. provided in the notice of references cited).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ikawa et al. (US Patent No. 9,711,530 B1), hereafter referred to as Ikawa.
As to claim 2, Jang discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the first insulating film is a SiO2 film (col. 5, lines 17-30),
the second insulating film is a SiOxN1-x film (col. 5, lines 41-53),
the third insulating film is a SiO2 film (col. 6, line 1).
Jang does not disclose wherein x of the SiOxN1-x film is a value in a range of 0.2 or more and 0.41 or less.
Nonetheless, Ikawa discloses wherein x of a SiOxN1-x film is a value in a range of 0.2 or more and 0.41 or less (col. 9, lines 11-38).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to optimize the oxygen content in the silicon oxynitride film of Jang to the value taught by Ikawa since this will optimize the etch resistance relative to silicon oxide layers.
As to claim 7, Jang discloses the method of manufacturing the semiconductor device according to claim 6 (paragraphs above),
wherein the first insulating film is a SiO2 film (col. 5, lines 17-30),
the second insulating film is a SiOxN1-x film (col. 5, lines 41-53),
the third insulating film is a SiO2 film (col. 6, line 1).
Jang does not disclose wherein x of the SiOxN1-x film is a value in a range of 0.2 or more and 0.41 or less.
Nonetheless, Ikawa discloses wherein x of a SiOxN1-x film is a value in a range of 0.2 or more and 0.41 or less (col. 9, lines 11-38).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to optimize the oxygen content in the silicon oxynitride film of Jang to the value taught by Ikawa since this will optimize the etch resistance relative to silicon oxide layers.
Claim(s) 3 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ikawa and further in view of Chin et al. (US Pub. No. 2023/0275024 A1), hereafter referred to as Chin.
As to claim 3, Jang in view of Ikawa disclose the semiconductor device according to claim 2 (paragraphs above).
Jang in view of Ikawa wherein a line width of the second wiring and an interval between adjacent second wirings are in a range of 10 nm or more and 50 nm or less.
Nonetheless, Chin discloses a line width of the second wiring and an interval between adjacent second wirings are in a range of 10 nm or more and 50 nm or less ([0078]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to make the line width of Jang in view of Ikawa in the range taught by Chin since this allows for improved electrical connectivity between the semiconductor device components.
As to claim 8, Jang in view of Ikawa disclose the method of manufacturing the semiconductor device according to claim 7 (paragraphs above).
Jang in view of Ikawa wherein a line width of the second wiring and an interval between adjacent second wirings are in a range of 10 nm or more and 50 nm or less.
Nonetheless, Chin discloses a line width of the second wiring and an interval between adjacent second wirings are in a range of 10 nm or more and 50 nm or less ([0078]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to make the line width of Jang in view of Ikawa in the range taught by Chin since this allows for improved electrical connectivity between the semiconductor device components.
Claim(s) 4 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ikawa and further in view of Totsuka (US Pub. No. 2020/0243266 A1).
As to claim 4, Jang in view of Ikawa disclose the semiconductor device according to claim 2 (paragraphs above).
Jang in view of Ikawa do not disclose wherein the dielectric strength voltage between the adjacent second wirings is 7MV/cm or more.
However, Jang discloses silicon dioxide between adjacent second wiring (136; as such, in this region silicon dioxide having a dielectric strength voltage of 10MV/cm).
Furthermore, Totsuka discloses wherein a dielectric strength voltage of silicon oxynitride is 7MV/cm or more ([0026] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to optimize the oxygen concentration in the silicon oxynitride of Jang in view of Ikawa such that the dielectric strength of the insulating layer is large as taught by Totsuka since this will decrease parasitic effects of the wiring layers.
As to claim 9, Jang in view of Ikawa disclose the method of manufacturing the semiconductor device according to claim 7 (paragraphs above).
Jang in view of Ikawa do not disclose wherein the dielectric strength voltage between the adjacent second wirings is 7MV/cm or more.
However, Jang discloses silicon dioxide between adjacent second wiring (136; as such, in this region silicon dioxide having a dielectric strength voltage of 10MV/cm).
Furthermore, Totsuka discloses wherein a dielectric strength voltage of silicon oxynitride is 7MV/cm or more ([0026] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to optimize the oxygen concentration in the silicon oxynitride of Jang in view of Ikawa such that the dielectric strength of the insulating layer is large as taught by Totsuka since this will decrease parasitic effects of the wiring layers.
Claim(s) 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ikawa, Chin and further in view of Totsuka.
As to claim 5, Jang in view of Ikawa and Chin disclose the semiconductor device according to claim 3 (paragraphs above).
Jang in view of Ikawa do not disclose wherein the dielectric strength voltage between the adjacent second wirings is 7MV/cm or more.
However, Jang discloses silicon dioxide between adjacent second wiring (136; as such, in this region silicon dioxide having a dielectric strength voltage of 10MV/cm).
Furthermore, Totsuka discloses wherein a dielectric strength voltage of silicon oxynitride is 7MV/cm or more ([0026] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to optimize the oxygen concentration in the silicon oxynitride of Jang in view of Ikawa such that the dielectric strength of the insulating layer is large as taught by Totsuka since this will decrease parasitic effects of the wiring layers.
As to claim 10, Jang in view of Ikawa and Chin disclose the method of manufacturing the semiconductor device according to claim 8 (paragraphs above).
Jang in view of Ikawa do not disclose wherein the dielectric strength voltage between the adjacent second wirings is 7MV/cm or more.
However, Jang discloses silicon dioxide between adjacent second wiring (136; as such, in this region silicon dioxide having a dielectric strength voltage of 10MV/cm).
Furthermore, Totsuka discloses wherein a dielectric strength voltage of silicon oxynitride is 7MV/cm or more ([0026] and [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to optimize the oxygen concentration in the silicon oxynitride of Jang in view of Ikawa such that the dielectric strength of the insulating layer is large as taught by Totsuka since this will decrease parasitic effects of the wiring layers.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2007/0154674A1 US 2002/0140056A1 and US Pub. No. 2004/0227242A1.
Conclusion
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/6/2026