DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4,7-9 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2017/0250180 A1 to Lee, “Lee”, in view of U.S. Patent Application Publication Number 2019/0164993 A1 to Shimbo, “Shimbo”, and further in view of U.S. Patent Application Publication Number 2022/0139911 A1 to Wei et al., “Wei”.
Regarding claim 1, Lee discloses a semiconductor device (e.g. FIG. 29), comprising: first (10, ¶ [0022],[0149]) and second (12) transistors on a substrate (100, ¶ [0150],[0151]); and an isolation transistor (dummy transistor 14, ¶ [0149],[0152],[0167]) provided between the first (10) and second (12) transistors.
Lee fails to clearly teach a contact connected to a power line and the dummy gate electrode of the isolation transistor.
Shimbo teaches (FIG. 1, FIG. 1 enlarged view of W from FIG. 1) incorporating isolation transistors (e.g. filler cells, ¶ [0032]-[0037], including using isolations transistors in a capacitance cell ¶ [0071]-[0074]) and teaches (FIG. 9A) a contact (85c, ¶ [0073]) connected to a power line (ground potential VSS, ¶ [0037], Applicant teaches power line VPR1 connected source voltage VSS (i.e. ground voltage)) and to the dummy gate (91).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Lee with the isolation/dummy transistor as part of a capacitance cell as taught by Shimbo in order to make manufacturing the device easy (Shimbo Abstract, ¶ [0007]) for instance by reducing process induced variation in the semiconductor integrated circuit device and improve yield (Shimbo ¶ [0009]) and with the gate connected to a power supply voltage rather than floating in order to achieve more stable operations (Shimbo ¶ [0071]).
Shimbo fails to clearly teach wherein the power line is a lower power line in a lower portion of the substrate and therein the contact to the dummy gate is a back-side contact penetrating the substrate.
Wei teaches (e.g. FIG. 4E) a lower power line (482, ¶ [0128]) in a lower portion of a substrate (dielectric 480 formed in FIG. 4D, ¶ [0127]) and wherein a gate (e.g. 371-2, ¶ [0124]) includes backside gate contact (483, ¶ [0125]-[0128]) penetrating the substrate (480).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Lee in view of Shimbo with the backside contact as taught by Wei in order to desirably reduce the cell size as compared to conventional only front-side contacts (Wei ¶ [0002],[0015]-[0016]).
Regarding claim 2, Lee in view of Shimbo and Wei yields the semiconductor device of claim 1, and Lee further teaches (FIG. 29, or FIG. 30) wherein the isolation transistor (14) comprises: a channel pattern (180, ¶ [0161],[0163],[0165]) on the substrate (100), the channel pattern (180) comprising a plurality of semiconductor patterns (three as pictured in FIG. 29, two in FIG. 30), which are stacked and spaced apart from each other;
a gate insulating layer (154c, ¶ [0163]) interposed between the dummy gate electrode (162c, ¶ [0163]) and the channel pattern (180); and source and drain patterns (148b and 148c, ¶ [0176],[0178]) connected to different portions (left and right portions) of the channel pattern, wherein the dummy gate electrode (162c) comprises a plurality of inner electrodes, which are respectively interposed between the semiconductor patterns (180).
Wei further teaches (FIG. 4E) wherein the back-side gate contact (483) is in direct contact (exposed in FIG. 4A opening 479) with the lowermost (upwards is -z direction) one of the inner electrodes (gate dielectric 374, gate electrode material 372, ¶ [0095]).
Regarding claim 3, Lee in view of Shimbo and Wei yields the semiconductor device of claim 2, and Wei further teaches (FIG. 4E) wherein the lower power line (482) is vertically overlapped with the channel pattern (channels 475-1,475-2,475-3).
Regarding claim 4, although Lee in view of Shimbo and Wei yields the semiconductor device of claim 2 as discussed above, Lee fails to clearly teach a back-side active contact that penetrates the substrate and connects one of the source and drain patterns to the lower power line.
However, Wei further teaches (FIG. 3R,3S) a back-side active contact (383, ¶ [0108]) that penetrates the substrate (replacement dielectric 380, ¶ [0106]) and connects one of the source and drain patterns (“S/D” material 366 from FIG. 3I, ¶ [0089]) to a lower power line (382, ¶ [0111]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Lee in view of Shimbo and Wei with a back-side active contact to the power line as taught by Wei in order to desirably reduce the cell size as compared to conventional only front-side contacts (Wei ¶ [0002],[0015]-[0016]).
Regarding claim 7, Lee in view of Shimbo and Wei yields the semiconductor device of claim 1, and Shimbo further teaches wherein the lower power line (VSS, lower when applying teachings of Wei) is configured to apply a ground voltage (VSS, ¶ [0037]) to the back-side gate contact (when applying teachings of Wei).
Regarding claim 8, Lee in view of Shimbo and Wei yields the semiconductor device of claim 1, and Lee further teaches (e.g. FIG. 29) wherein the first (10) and second (12) transistors comprise first (166a, ¶ [0155],[0030],[0031]) and second (166b, ¶ [0158],[0050],[0051]) gate electrodes, respectively, and the dummy gate electrode (162c) is spaced apart from the first (162a) and second gate electrodes by substantially the same distance (as pictured).
Regarding claim 9, Lee in view of Shimbo and Wei yields the semiconductor device of claim 1, and Wei further teaches wherein the substrate is an insulating substrate (replacement dielectric 480 formed in FIG. 4D, ¶ [0127]).
Allowable Subject Matter
Claims 10-20 are allowed.
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Prior art e.g. Lee and Shimbo discuss dummy/filler transistors as discussed above, and prior art e.g. Wei generally teaches forming back-side active and back-side gate contacts as discussed above.
Prior art generally teaches forming dummy transistors with the gate connected to the source or drain and connected to a power or ground in order to form decoupling capacitors and reduce floating behavior e.g. U.S. Patent Application Publication Number 2005/0116268 A1 to Tahira et al. FIG. 4B dummy transistors PTr1 and NTr1 shorted to VDD and GND(VSS) respectively, Abstract, ¶ [0067],[0068]).
However, prior art fails to reasonably teach wherein a portion of a side surface of the back-side active contact is in contact with a portion of a side surface of the back-side gate contact as claimed in claim 5 together with all of the limitations of claims 4, and claim 2 and claim 1 upon which claim 5 depends. Similarly, prior art fails to reasonably teach or suggest wherein the back-side gate contact is in contact with one of the source and drain patterns as claimed in claim 6 together with all of the limitations of claim 2 and all of the limitations of claim 1 upon which claim 6 depends.
Prior art e.g. U.S. Patent Application Publication Number 2021/0075406 to Kim et al. teaches (FIG. 1, FIG. 3) forming a filler cell or dummy cell (FC, ¶ [0033]) between inverters (flip-flops FF1-FF4)
However, prior art fails to reasonably teach or suggest an isolation circuit provided between the first inverter and the second inverter, wherein the isolation circuit comprises: first source/drain patterns on the first active region; a first dummy gate electrode provided between the first source/drain patterns and crossing the first active region; second source/drain patterns on the second active region; a second dummy gate electrode provided between the second source/drain patterns, crossing the second active region and spaced apart from the first dummy gate electrode in the first direction; a first back-side gate contact penetrating the substrate and directly connected to the first lower power line and the first dummy gate electrode; and a second back-side gate contact penetrating the substrate and directly connected to the second lower power line and the second dummy gate electrode, together with all of the limitations of claim 10 as claimed. Claim 20 is allowable for similar reasons to claim 10 and claims 11-19 are allowable insofar as they depend upon and include all of the limitations of allowable claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
Prosecution Insights