DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 7, 2023, March 1, 2024, May 9, 2024, November 24, 2025, January 21, 2026, May 5, 2026 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on April 9, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui (US Pat. No. 10,304,852). Claim 1, Cui discloses (Figs. 3-28C) a memory device, comprising: an alternating stack of insulating layers (Fig. 24, 132/232, insulating layers, Col. 36, lines: 40-45) and electrically conductive layers (Fig. 24, 146/246, electrically conductive layers, Col. 36, lines: 40-45), the alternating stack comprising stepped surfaces (Fig. 24, 132/232 and 146/246 have stepped surface at staircase region 200, Col. 36, lines: 45-47); a memory opening (Fig. 24, opening where memory opening fill structure 58 is formed, hereinafter “opening”) vertically extending through each layer within the alternating stack (opening vertically extends through 132/232 and 146/246); a memory opening fill structure (Fig. 24, 58, memory opening fill structure, Col. 24, lines: 42-25) located in the memory opening (58 is in opening) and comprising (labeled in Fig. 11) a vertical stack of memory elements (Fig. 11, 50, memory film, Col. 24, lines: 34-40) and a vertical semiconductor channel (Fig. 11, 60, vertical semiconductor channel, Col. 24, lines: 34-40); a dielectric material layer (Fig. 24, 165/265, retro-stepped dielectric material portions, Col. 26. lines: 1-10) that extends from a bottommost vertical step of the stepped surfaces to a topmost vertical step of the stepped surfaces (165/265 extends from bottommost step to topmost step in stepped surface of region 200); and a contact via structure (Fig. 28C, 86, column-shaped conductive via structure, Col. 36, lines: 1-10) comprising: an upper contact via portion (Fig. 28C, left 86P, conductive capital portion, Col. 35, lines: 10-18) having an annular bottom surface (Fig. 28B shows 86 has an annular top surface since it’s a cylindrical shape, so 86P would have annular bottom surface) that contacts an annular top surface (since left 86P contacts topmost 146, top surface of 146 would be annular) of a first electrically conductive layer (topmost 146) of the electrically conductive layers (146/246); and a lower contact via portion (Fig. 28C, left 86S, conductive shaft portion, Col. 35, lines: 9-20) that vertically extends through a first subset of the electrically conductive layers (left 86S vertically extends through a subset of 146 under topmost 146, hereinafter “subset1”) that underlie the first electrically conductive layer (subset1 underlies topmost 146), wherein the lower contact via portion is narrower than the upper contact via portion (left 86S is narrower than left 86P).
Claim 2, Cui discloses (Figs. 3-28C) the memory device of Claim 1, wherein the upper contact via portion (Fig. 28C, left 86P) comprises a sidewall (topmost right sidewall) that contacts a cylindrical sidewall of an opening in the dielectric material layer (as can be seen in Fig. 28C the topmost right sidewall of left 86P contacts a sidewall of 165 where an opening would be formed and 165 would have a cylindrical shape). Claim 3, Cui discloses (Figs. 3-28C) the memory device of Claim 1, wherein the dielectric material layer (165/265) has a different material composition (132/232 can be undoped silicon oxide, Col. 15, lines: 60-65, Col. 16, lines: 1-10, 165/265 can be doped silicon oxide, Col. 26, lines: 33-45) than the insulating layers (132/232).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui (US Pat. No. 10,304,852) as applied to claim 3 above, and further in view of Kasai (US 2021/0327897). Claim 4, Cui discloses (Figs. 3-28C) the memory device of Claim 3, wherein the insulating layers (132/232) comprise silicon oxide (132/232 can be doped or undoped silicon oxide, Col. 15, lines: 60-65, Col. 16, lines: 1-10).
Cui does not explicitly disclose the dielectric material layer comprises silicon oxycarbide. However, Kasai discloses (Fig. 27) a retro-stepped dielectric material portion 64 may comprise silicon oxycarbide (Para [00308]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Kasai, including the specific material of the retro-stepped dielectric layer to the teachings of Cui.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as a retro-stepped dielectric material as silicon oxycarbide has significantly higher etch resistance in comparison to silicon oxide (Para [0308]).
Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
Allowable Subject Matter
Claims 5-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Cui (US Pat. No. 10,304,852), Kasai (US 2021/0327897), Kaminaga (US Pat. No. 10,727,248), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 5 (from which claims 6-13 depend), Cui discloses (Figs. 3-28C) a memory device, comprising: an alternating stack of insulating layers (Fig. 24, 132/232, insulating layers, Col. 36, lines: 40-45) and electrically conductive layers (Fig. 24, 146/246, electrically conductive layers, Col. 36, lines: 40-45), the alternating stack comprising stepped surfaces (Fig. 24, 132/232 and 146/246 have stepped surface at staircase region 200, Col. 36, lines: 45-47); a memory opening (Fig. 24, opening where memory opening fill structure 58 is formed, hereinafter “opening”) vertically extending through each layer within the alternating stack (opening vertically extends through 132/232 and 146/246); a memory opening fill structure (Fig. 24, 58, memory opening fill structure, Col. 24, lines: 42-25) located in the memory opening (58 is in opening) and comprising (labeled in Fig. 11) a vertical stack of memory elements (Fig. 11, 50, memory film, Col. 24, lines: 34-40) and a vertical semiconductor channel (Fig. 11, 60, vertical semiconductor channel, Col. 24, lines: 34-40); a dielectric material layer (Fig. 24, 165/265, retro-stepped dielectric material portions, Col. 26. lines: 1-10) that extends from a bottommost vertical step of the stepped surfaces to a topmost vertical step of the stepped surfaces (165/265 extends from bottommost step to topmost step in stepped surface of region 200); and a contact via structure (Fig. 28C, 86, column-shaped conductive via structure, Col. 36, lines: 1-10) comprising: an upper contact via portion (Fig. 28C, left 86P, conductive capital portion, Col. 35, lines: 10-18) having an annular bottom surface (Fig. 28B shows 86 has an annular top surface since it’s a cylindrical shape, so 86P would have annular bottom surface) that contacts an annular top surface (since left 86P contacts topmost 146, top surface of 146 would be annular) of a first electrically conductive layer (topmost 146) of the electrically conductive layers (146/246); and a lower contact via portion (Fig. 28C, left 86S, conductive shaft portion, Col. 35, lines: 9-20) that vertically extends through a first subset of the electrically conductive layers (left 86S vertically extends through a subset of 146 under topmost 146, hereinafter “subset1”) that underlie the first electrically conductive layer (subset1 underlies topmost 146), wherein the lower contact via portion is narrower than the upper contact via portion (left 86S is narrower than left 86P).
Cui does not disclose: further comprising a stepped dielectric material portion overlying the dielectric material layer, wherein the upper contact via portion vertically extends through the stepped dielectric material portion.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kaminaga (US Pat. No. 10,727,248) discloses (Fig. 28C) a contact via 86 with an upper 86P and lower 86S portions. Kaminaga does not disclose a stepped dielectric material portion overlying the dielectric material layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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