Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 5 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (US 2018/0374791, hereinafter Smith) in view of Su et al. (US 2021/0391325, hereinafter Su).
With respect to claim 1, Smith discloses a semiconductor device (Fig. 1) comprising: a substrate (Para 0003 – substrate) which includes an upper side and a lower side that are opposite to each other (top & bottom sides of the substrate); first and second active patterns which each extend in a first direction and are spaced apart from each other in a second direction (Fig. 1 – there are multiple patterns extending vertically and spaced apart from each other in horizontal direction);
a field insulating film (STI oxide of Fig. 2) which covers side walls of the first and second active patterns (fig. 2); a power rail which is disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern (para 0010-0011; Fig. 13 - – buried power rails are formed between active fins and are adjacent to side walls); a power rail via which is disposed on the power rail and connected to the power rail (para 0016 – via structures to connect with the power rails); a semiconductor etching stop pattern which is disposed adjacent to a second side wall of the second active pattern (Para 0023- SiGe layer controlling etching); and a first semiconductor pattern (Para 0033 – SiGe channel/nanosheets) disposed on the semiconductor etching stop pattern (Para 0023 & 0033), and wherein at least part of the first semiconductor pattern is disposed in the field insulating film (Para 0023; 0033 – SiGe channel/nanosheets are in STI).
Smith does not explicitly disclose wherein a lower surface of the semiconductor etching stop pattern is disposed on a same plane as the lower side of the substrate.
In an analogous art, Su discloses wherein a lower surface of the semiconductor etching stop pattern is disposed on a same plane as the lower side of the substrate (Para 0019; 0022, 0025, and 0035- after planarization from the backside, the bottom surface of the etch stop is coplanar with the backside surface of the substate). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith’s device by having Su’s disclosure in order to remove excess material to form backside contacts.
With respect to claim 5, Smith does not politicly disclose wherein an upper surface of the semiconductor etching stop pattern and an upper surface of the power rail are on a same plane.
In an analogous art, Su discloses wherein an upper surface of the semiconductor etching stop pattern and an upper surface of the power rail are on a same plane (Para 0019; 0022, 0025, and 0035- after planarization, the top surface of the etch stop is coplanar with the upper surface of the power rail). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith’s device by having Su’s disclosure in order to remove excess material to form backside contacts.
With respect to claim 10, Smith does not explicitly disclose wherein at least a part of the semiconductor etching stop pattern is disposed in the field insulating film.
In an analogous art, Su discloses wherein at least a part of the semiconductor etching stop pattern (213 of Fig. 11B) is disposed in the field insulating film (215 & 224 - Para 0019). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith’s device by having Su’s disclosure in order to remove excess material to form backside contacts.
With respect to claim 11, Smith does not explicitly disclose wherein the semiconductor etching stop pattern does not completely overlap the field insulating film in the first direction and the second direction.
In an analogous art, Su discloses wherein the semiconductor etching stop pattern does not completely overlap the field insulating film in the first direction and the second direction (Fig. 16 B – 232 does not completely overlap 203). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith’s device by having Su’s disclosure in order to remove excess material to form backside contacts.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Smith/Su in view of Sue et al. (US 2021/0313319, hereinafter Sue).
With respect to claim 2, Smith/Su does not explicitly disclose a plurality of gate electrodes which each extend in the second direction and are spaced apart from each other in the first direction, on the first and second active patterns, wherein the power rail via is disposed between the plurality of gate electrodes.
In an analogous art, Sue discloses a plurality of gate electrodes which each extend in the second direction and are spaced apart from each other in the first direction, on the first and second active patterns, wherein the power rail via is disposed between the plurality of gate electrodes (Para 0041- 0042; 0071). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith/Su’s device by having Sue’s disclosure in order to achieve the optimal results by routing adjustments.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Smith/Su in view of Kim et al. (US 2020/0373331, hereinafter Kim).
With respect to claim 3, Smith/Su does not explicitly disclose a lower insulating film disposed on the lower side of the substrate, wherein the power rail penetrates the lower insulating film.
In an analogous art, Kim discloses a lower insulating film (105 of fig. 6B - 7) disposed on the lower side of the substrate, wherein the power rail penetrates the lower insulating film (Fig. 15, Para 0128 – buried power rail). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith/Su’s device by having Kim’s disclosure in order to isolate different components of a semiconductor device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Smith/Su in view of Xie et al. (US 2023/0402318, hereinafter Xie).
With respect to claim 12, Smith discloses etch stop layer comprises of SiGe.
(Para 0023- SiGe layer controlling etching).
Smith/Su does not explicitly disclose wherein the semiconductor etching stop pattern and the first semiconductor pattern are formed of different materials from each other.
In an analogous art, Xie discloses wherein the semiconductor etching stop pattern and the first semiconductor pattern are formed of different materials from each other (para 0044; 0064 – nanosheets can be silicon and etch stop layer can comprise of silicon nitride or SiGe). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Smith/Su’s device by having Xie’s disclosure in order to isolate different components of a semiconductor device.
Allowable Subject Matter
Claims 4, and 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 4, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the semiconductor etching stop pattern is in contact with the lower insulating film” when considered as a whole along with other claimed limitations.
With respect to claim 6, none of the prior art on record disclose or render obvious the claimed limitations including “wherein a first height of the upper surface of the semiconductor etching stop pattern based on the lower side of the substrate is greater than a second height of a lower surface of the power rail via based on the lower side of the substrate”. when considered as a whole along with other claimed limitations.
With respect to claim 7, none of the prior art on record disclose or render obvious the claimed limitations including “ a second semiconductor pattern disposed on an upper surface of the power rail via , wherein the power rail via penetrates the second semiconductor pattern and is connected to the power rail” when considered as a whole along with other claimed limitations.
Claims 8-9 have been objected because of their dependency on claim 7.
Claims 13-20 have been allowed.
With respect to claim 13, none of the prior art on record disclose or render obvious the claimed limitations including “a power rail via which is disposed between the plurality of gate electrodes, and between the first source/drain pattern and the second source/drain pattern, wherein the power rail via is disposed on the power rail and is connected to the power rail; a first semiconductor etching stop pattern which is disposed between the second active pattern and the third active pattern; and a semiconductor pattern disposed on the first semiconductor etching stop pattern, wherein a first spaced distance in the second direction between the first active pattern and the second active pattern is greater than a second spaced distance in the second direction between the second active pattern and the third active pattern, a lower surface of the first semiconductor etching stop pattern is disposed on the lower insulating film, and at least part of the semiconductor pattern overlaps the field insulating film” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 19, none of the prior art on record disclose or render obvious the claimed limitations including “a second source/drain pattern which is connected to the second sheet pattern and is disposed between the plurality of gate electrodes, on the second lower pattern; a power rail which is placed between the first lower pattern and the second lower pattern, on the lower side of the substrate; a power rail via which is placed between the first and second source/drain patterns and between the plurality of gate electrodes, wherein the power rail via is connected to the power rail; a semiconductor etching stop pattern which is placed adjacent to a first side wall of the second lower pattern that is opposite to a second sidewall of the second lower pattern that faces the first lower pattern; and a semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is placed on a same plane as the lower side of the substrate, at least a part of the semiconductor pattern overlaps the field insulating film in the third direction, and the semiconductor etching stop pattern and the semiconductor pattern are formed of different materials from each other” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 14-18 and 20 are allowable because of their dependency on claims 13 and 19 respectively.
Conclusion
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/MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899
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