DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Figs. 1-4) corresponding to claims 1-3, 9-12 and 17-18 in the reply filed on 11/03/2025 is acknowledged. Claims 4-8, 13-16 and 19-20 have been withdrawn from consideration in this Office Action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/07/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 9, 10, 12 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamoto (US 2023/0066061 A1).
Regarding claim 1, Nakamoto discloses a charge-to-voltage conversion circuit (Figs. 3-6 & 11) comprising:
a first transistor (transistor 255 in Fig. 4) powered by a supply voltage and configured, when activated by a bias current (from the bias current source 327 in Fig. 6 that connects to transistor 255 by column line 259), to produce an output voltage based on a charge received at a gate of the first transistor (Figs. 4, 6 & 11 and par. [0075], [0083]-[0084]. Note that transistor 255 is a source follower which is activated by the bias current source 327 connected to the column line during readout of the output voltage);
a biasing current source (327 in Figs. 6 & 11) electrically connected to the first transistor and configured to generate the bias current to activate the first transistor (Figs. 4 & 6 and par. [0075], [0083]-[0084]); and
an inline amplifier stage (column amplifier) including a second transistor (322), the inline amplifier stage being positioned between the first transistor (255) and the biasing current source (327) and being configured to use the bias current generated by the biasing current source to activate the second transistor (322) to amplify the output voltage on an output voltage node of the charge-to-voltage conversion circuit (see Figs. 6 & 11 and par. [0081]-[0087]. It should be noted that the inline amplifier is mainly considered as containing transistor 322, switch 324 and capacitors 325 & 326, and the transistor 322 is activated by the current source).
Regarding claim 3, Nakamoto further discloses that the inline amplifier stage is configured to amplify the output voltage with a closed-loop gain (by the feedback circuit shown in Fig. 6) produced using: a first capacitor (325) electrically connected between a gate of the second transistor and the output voltage node; and a second capacitor (326) electrically connected between the gate of the second transistor and a ground (Fig. 6 and par. [0086]-[0087]).
Regarding claim 9, Nakamoto discloses an active pixel sensor (APS) readout circuit (Figs. 3-6 & 11) comprising:
a floating diffusion transistor (255 in Figs. 4 & 11) powered by a supply voltage and configured, when activated by a bias current, to produce an output voltage based on a charge detected by a light detection element associated with a pixel of an array of pixels (Figs. 4 & 6 and par. [0073]-[0075], [0083]-[0084] and also note the Examiner’s comments in claim 1);
a biasing current source (327 in Figs. 6 & 11) electrically connected to the floating diffusion transistor (255) and configured to generate the bias current to activate the floating diffusion transistor (par. [0073]-[0075], [0083]-[0084] and also note the Examiner’s comments in claim 1);
a row select transistor (256 in Figs. 4 & 11) configured, when enabled, to connect the output voltage onto a shared pixel readout node (column node of vertical readout line 259) associated with a column of the pixel within the array of pixels (Figs. 3 & 4 and par.[0062]-[0065], [0073]-[0075], wherein the vertical readout line 259 is shared among rows of pixels, and hence “a shared pixel readout node” is met); and
an inline amplifier stage (column amplifier) positioned between the floating diffusion transistor (255) and the biasing current source (327), the inline amplifier stage configured to use the bias current generated by the biasing current source to activate an amplifier transistor within the inline amplifier stage to amplify the output voltage on an output voltage node of the APS readout circuit (see Figs. 4, 6 & 11, par. [0081]-[0087] and note the Examiner’s comments in claim 1).
Regarding claim 10, as also disclosed by Nakamoto in Figs. 3-7, the output voltage node is electrically connected to a load circuit (Fig. 7); and the load circuit includes an analog-to-digital converter circuit that is configured to receive the amplified output voltage and to produce, based on the amplified output voltage, a digital value (see par. [0089]-[0094]).
Regarding claim 12, the subject matter of this claim is also met by Nakamoto as discussed in claim 3.
Regarding claim 17, the subject matter of this claim is also met by Nakamoto as discussed in claims 1 and 9.
Allowable Subject Matter
Claims 2, 11 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art references of record fail to teach or suggest or render obviousness of: “the inline amplifier stage includes a body bias current source electrically connected to the second transistor and configured to draw current from a body of the second transistor.”
Regarding claim 11, this claim recites similar limitations as claim 2 and is therefore allowed for the same reason stated above.
Regarding claim 18, the prior art references of record also fail to teach or suggest or render obviousness of: “comprising drawing current, by a body bias current source electrically connected to the amplifier transistor within the inline amplifier stage, from a body of the amplifier transistor; wherein the inline amplifier stage amplifies the output voltage with a closed-loop gain produced using: a first capacitor electrically connected between a gate of the amplifier transistor and the output voltage node; and a second capacitor electrically connected between the gate of the amplifier transistor and a ground.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHAN T TRAN whose telephone number is (571)272-7371. The examiner can normally be reached Monday - Friday, 9:00am - 5:00pm.
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/NHAN T TRAN/ Primary Examiner, Art Unit 2638