DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 9-20 are allowed.
With respect to claim 9, the prior art fails to teach in combination with the rest of the limitations in the claim: “a wiring structure arranged in an edge of the semiconductor chip,
a clock counter configured to output a test signal to a first node of the wiring
structure in response to the test command signal received from the controller and
receive the test signal from a second node of the wiring structure, and
an oscillator configured to output a first clock signal to the clock counter, and
wherein the clock counter is configured to count a number of clocks of the first clock
signal as a first count value from a first time in which the test signal is output to the first node
of the wiring structure to a second time in which the test signal is received from the second
node of the wiring structure, and output a first resultant signal to the controller based on the
first count value.”
With respect to claim 19, the prior art fails to teach in combination with the rest of the limitations in the claim: “a controller configured to output a test command signal to the plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises: a wiring structure arranged in an edge of the semiconductor chip,
a clock counter configured to output a test signal to a first node of the wiring
structure in response to the test command signal and receive the test signal from a
second node of the wiring structure, and
an oscillator configured to output a first clock signal to the clock counter, and
wherein the clock counter is configured to count a number of clocks of the first clock
signal as a first count value from a first time in which the test signal is output to the first node
of the wiring structure to a second time in which the test signal is received from the second
node of the wiring structure, and output a first resultant signal to the controller based on the
first count value.”
Claims 10-12 and 15 are allowable due to their dependencies on claim 9; claim 13 is allowable due to its dependency on claim 12; claim 14 is allowable due to its dependency on claim 13; claim 16 is allowable due to its dependency on claim 15; claim 17 is allowable due to its dependency on claim 16; claim 18 is allowable due to its dependency on claim 17; claim 20 is objected to due to its dependency on claim 19.
Claims 5, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 5, the prior art fails to teach in combination with the rest of the limitations in the claim: “output the first resultant signal having a first resultant value to the controller based on a determination the first count value is greater than or equal to a first reference value, and output the first resultant signal having a second resultant value to the controller based on a
determination the first count value is less than the first reference value.”
With respect to claim 7, the prior art fails to teach in combination with the rest of the limitations in the claim: “wherein the sub clock counter is configured to count a number of clocks of the first clock signal, as a second count value, from a third time in which the test signal is input to the first node of the wiring structure by the clock counter to a fourth time in which the test signal is received from the third node of the wiring structure, and output a second resultant signal to the controller based on the second count value.”
Claim 8 is objected to due to its dependency on claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (U.S. Patent No. 10,168,387 B2).
With respect to claim 1, Lim et al. discloses a semiconductor chip comprising:
a wiring structure arranged along an edge of the semiconductor chip (see semiconductor wafer 100 shown in Fig. 1);
a clock counter configured to output a test signal to a first node of the wiring structure
and receive the test signal from a second node of the wiring structure (col. 1, lines 31-37); and
an oscillator configured to output a first clock signal to the clock counter (col. 1, lines 31-37),
wherein the clock counter is configured to count a number of clocks of the first clock
signal as a first count value from a first time in which the test signal (col. 6, lines 47-53) is output to the first node of the wiring structure to a second time in which the test signal is received from the second node of the wiring structure (col. 6, lines 54-62), and output a first resultant signal to a controller based on the first count value (col. 8, lines 9-14).
With respect to claim 2, Lim et al. discloses the semiconductor chip of claim 1, further comprising a clock generator configured to output a second clock signal to the clock counter (see clock signal lines 124 coupling registers 120 with one another; col. 8, lines 9-14),
wherein the clock counter is configured to generate the test signal based on the second
clock signal (col. 4, lines 22-29).
With respect to claim 3, Lim et al. discloses the semiconductor chip of claim 1, wherein the clock counter is configured to output the test signal to the first node of the wiring structure in response to a test command signal received by the clock counter from the controller (see control circuitry 118 shown in Fig. 1).
With respect to claim 4, Lim et al. discloses the semiconductor chip of claim 1, wherein the oscillator comprises a frequency control circuit for adjusting a frequency of the first clock signal (col. 4, lines 53-59).
With respect to claim 6, Lim et al. discloses the semiconductor chip of claim 1, further comprising a sub clock counter configured to receive the test signal from a third node of the wiring structure and receive the first clock signal from the oscillator (col. 9, lines 27-35; oscillator 142 (VCO)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARHANA AKHTER HOQUE whose telephone number is (571)270-7543. The examiner can normally be reached Monday-Friday, 7:30am-4:00pm.
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/FARHANA A HOQUE/Primary Examiner, Art Unit 2858
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