DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-5, 7-8, 13-20 in the reply filed on 3/20/2026 is acknowledged.
Claims 6,9-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/20/2026
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, & 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2019/0103047 A1) in view of Kim (US Pub no. 2022/0367514 A1).
Regarding claim 1, Kim et al (‘047)discloses a semiconductor device, comprising:
a substrate(100) [0034]; semiconductor patterns(SP) that are stacked on the substrate(100) fig. 5[0035], extend in a first direction(D1) parallel to a top surface of the substrate(100) fig. 5, and are spaced apart from each other(fig. 5)[0035];
a gate electrode (WL)comprising horizontal portions, that extend in a second direction (D2)crossing the first direction(D1) , and a vertical portion, that is in contact with the horizontal portions and extends in a third direction (D3)perpendicular to the top surface of the substrate(100) fig. 5;
wherein each of the semiconductor patterns (SP)comprises impurity regions and a channel region between the impurity regions[0036], the vertical portion (WL)is on a first side surface of the channel region(CH), and the horizontal portions (WL)are on a top surface and a bottom surface of the channel region(CH) fig. 3b.
Kim et al (‘047)discloses a gate insulating layer (GI-multilayered structure including a ferroelectric layer lead zinc niobate)between the semiconductor patterns(SP ) and the gate electrode(WL) fig. 5[0049]; but fails to teach a ferroelectric layer between the gate insulating layer and the gate electrode.
However, Kim et al (‘514) teaches a ferroelectric layer(DSP1a) between the gate insulating layer (GiLa)and the gate electrode(Wla)[0052-0053][0057]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al (‘047) with the teachings of Kim et al (‘514) to maintain polarization state.
Regarding claim 2, Kim et al(‘047) discloses wherein the gate insulating layer(GI) is
in contact with the first side surface, the top surface, and the bottom surface of the channel region(CH) fig. 3b.
Regarding claim 4, Kim et al (‘047)discloses wherein the horizontal portions(WL) are
spaced apart from each other in the third direction(D3) fig. 3b.
Regarding claim 5, Kim et al(‘047) discloses further comprising an insulating pattern that is on a second side surface of the channel region(CH) that is opposite to the first side surface[0069](IL4 and IL5 are between SP ).
Regarding claim 13, Kim et al (‘047) discloses further comprising an interlayer
insulating pattern (IL4 and IL5)between two of the impurity regions (SD1/SD2)of the semiconductor patterns t(SP)hat are adjacent to each other in the third direction(D3)[0069] fig. 11a.
Allowable Subject Matter
Claims 3, 7, & 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 14-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach an outer ferroelectric layer between the outer gate electrode and the semiconductor patterns; and an inner ferroelectric layer between the inner gate electrode and the semiconductor patterns, wherein the horizontal portion extends between two of the semiconductor patterns that are adjacent to each other in the vertical direction.
. Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach a second gate structure on bottom surfaces, top surfaces, and outer side surfaces of the second semiconductor patterns,
wherein the first semiconductor patterns are spaced apart from the second semiconductor patterns in the second direction, and wherein the first gate structure and the second gate structure are symmetrical to each other in the second direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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