Prosecution Insights
Last updated: July 17, 2026
Application No. 18/532,551

RESISTIVE MEMORY WITH ANGLED ELECTRODE PROFILE

Non-Final OA §102§103§112
Filed
Dec 07, 2023
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
497 granted / 699 resolved
+3.1% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
23 currently pending
Career history
722
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
80.2%
+40.2% vs TC avg
§102
10.6%
-29.4% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 699 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This office action is in response to the election filed 3/25/2026. Currently, claims 1-20 are pending, of which claims 10-20 have been withdrawn from consideration. Election/Restrictions Applicant’s election without traverse of claims 1-9 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitation “planar sub-surface of the asymmetrical first electrode structure”. It is not clear what is meant by the term “subsurface”, which would generally be taken to mean something below a surface. However, in terms of the asymmetrical first electrode, this would apparently refer to an interior of the asymmetrical first electrode. There does not appear to be anything about the interior that could be described as “planar”. For purposes of examination, “subsurface” is taken to mean the bottom surface of the asymmetrical first electrode structure, which is planar. Claims 3 and 4 each recite the limitation “the direction”, which lacks antecedent basis. While “a direction” is recited in claim 2, neither of claims 3 or 4 depend on claim 2. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Walls et al. (US 9,412,942). Pertaining to claim 1, Walls shows, with reference to FIG. 4N1, a memory structure comprising: an asymmetrical first electrode structure (140) having a slanted surface (142); a memory switching layer (170) forming an interface with the slanted surface of the asymmetrical first electrode structure; and a second electrode structure (172) located on the memory switching layer. Pertaining to claim 2, Walls shows the slanted surface of the asymmetrical first electrode structure extends in a direction from a topmost surface down to a planar sub-surface (bottom surface) of the asymmetrical first electrode structure. Pertaining to claims 3 and 4, Walls shows the direction of the slant is left to right for some first electrodes, and right to left for others. Claims 1, 3-4 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0225936). Pertaining to claim 1, Wang shows, with reference to FIG. 8, a memory structure comprising: an asymmetrical first electrode structure (either of 802 or 804) having a slanted surface; a memory switching layer (106 or 108) forming an interface with the slanted surface of the asymmetrical first electrode structure; and a second electrode structure (110 or 112) located on the memory switching layer. Pertaining to claim 3, Wang shows the direction of the slant is from left to right (left structure). Pertaining to claim 4, Wang shows the direction of the slant is from right to left (right structure). Pertaining to claim 9, Wang shows the memory switch layer has a sidewall that is vertically aligned with a sidewall of the second electrode structure (shown in FIG. 8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Walls. Pertaining to claim 5, Walls shows a first electrically conductive layer (104) in electrical contact with the asymmetrical first electrode structure, and a via contact structure (180) that connects to the second electrode. Although Walls does not explicitly show a second electrically conductive layer to which the via connects the second electrode, it would be obvious to one of ordinary skill in the art for this to be the case as, otherwise, contact structure 180 would serve no purpose. In other words, the device would be inoperable without further connection from the second electrode to some other conductive line. Pertaining to claim 6, Walls shows an encapsulation layer (182) located adjacent to the memory switching layer, the second electrode structure and the via contact structure. Allowable Subject Matter Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach the limitations of claim 7 in combination with the limitations recited in claim 6 and the claims on which claim 6 depends. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Walls et al. (US 10,003,021) and Wu et al. (CN 104993049) disclose resistive memories with slanted bottom electrodes. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Dec 07, 2023
Application Filed
Apr 17, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684689
TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDS
4y 0m to grant Granted Jul 14, 2026
Patent 12685137
Wire Structure for Low Resistance Interconnects
3y 7m to grant Granted Jul 14, 2026
Patent 12660580
INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME
4y 3m to grant Granted Jun 16, 2026
Patent 12660586
VIA STRUCTURE AND METHODS FOR FORMING THE SAME
3y 11m to grant Granted Jun 16, 2026
Patent 12660581
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
3y 5m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+18.8%)
2y 9m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 699 resolved cases by this examiner. Grant probability derived from career allowance rate.

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