Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of group I in the reply filed on 05/04/2026 is acknowledged. The traversal is on the ground(s) that “claim 17 is not limited to a particular technique for forming the gate cut. Rather, claim 17 recites, "cutting the gate extension into portions by forming a gate cut through the gate extension to divide the gate extension.” The techniques identified by the Restriction Requirement appear to be examples of how the recited gate-cut forming step could be performed, rather than a showing that the claimed product can be made by another materially different process. Accordingly, the Restriction Requirement does not sufficiently establish distinctness between the alleged inventions.” This is not found persuasive because referring to the restriction requirement set forth in the previous office action, it clearly shows that the alternative method steps proposed by the examiner would be distinct from the process claimed, yet they all make the same device as claimed in claim 1. Applicant did not show the suggested alternative method steps were incorrect and has not provided a convincing argument that the materially different processes would not be suitable in producing the claimed device. As it was cited in the previous office action, “if the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse... Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103(a) of the other invention.” Additionally, it requires a different field of search; searching different classes/subclasses or electronic resources, or employing different search strategies or search queries, and the prior art applicable to one invention would not likely be applicable to another invention.
The requirement is still deemed proper and is therefore made FINAL. Currently, claims 1-16 are pending and claims 17-20 have been withdrawn from further consideration as they are drawn to the non-elected claims.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bouche et al. (Pub. No. US 2022/0157722 A1, herein Bouche).
Regarding claim 1, Bouche discloses a semiconductor device, comprising: a gate metal 212 (Figs. 2-4A and paragraph [0066]); a gate extension disposed within a region between two transistors of opposite conductivity types and connected to the gate metal ([0003] and [0080]), the gate extension extending toward a side of the semiconductor device having power rails (BPR, [0031]); a gate cut 318/312 disposed within the gate metal and through the gate extension to cut the gate extension into portions that are electrically isolated from each other ([0101]); and wherein each of the portions of the gate extension is coupled to a backside power rail (Figs. 4D-5B, 7L and [0077]).
Regarding claim 2, Bouche discloses the semiconductor device as recited in claim 1, wherein the gate extension is disposed within a shallow trench isolation 106 ([0084], [0109]).
Regarding claim 3, Bouche discloses the semiconductor device as recited in claim 1, wherein the portions of the gate extension are connected to corresponding local interconnects (Figs. 9-10 and [0111], [0125]).
Regarding claim 4, Bouche discloses the semiconductor device as recited in claim 3, wherein each of the local interconnects connects a corresponding portion of the gate extension to the backside power rail to which the corresponding portion of the gate extension is coupled (Figs. 9-10 and [0111], [0125]).
Regarding claim 5, Bouche discloses the semiconductor device as recited in claim 4, wherein the gate extension extends toward a back side of the semiconductor device, and the local interconnects are disposed within a layer for back side contacts (Figs. 4C, 7L and [0080], [0085]).
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Pub. No. US 2021/0020636 A1, herein Lee).
Regarding claim 8, Lee discloses a semiconductor device, comprising: an N-type field effect transistor (NFET) “I” ([0037]); a P-type field effect transistor (PFET) “II” disposed adjacent to the NFET (Figs. 4, 6 and [0037]); a gate metal “G3”/134 disposed in a region between the NFET and the PFET ([0043]-[0044]); a gate extension disposed within the region between the NFET and the PFET and connected to the gate metal on a back side of the semiconductor device (Figs. 10B, 11B, 12B, and [0043]-[0044]); and a gate cut “CT1/CT2/CT3” disposed through the gate metal, and through the gate extension to cut the gate extension into a first portion and a second portion to electrically isolate the first portion from the second portion ([0031], [0047]); and the first portion being coupled to a first backside power rail and the second portion being coupled to a second backside power rail ([0004], [0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Bouche.
Regarding claim 9, Lee does not specifically show the gate extension is disposed within a shallow trench isolation.
However, in the same field of endeavor, Bouche discloses a semiconductor device, wherein the gate extension is disposed within a shallow trench isolation 106 ([0084], [0109]) to electrically isolate neighboring transistors and other active regions.
Therefore, given the teachings of Bouche, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lee in view of Bouche by employing the shallow trench isolation.
Regarding claims 10-11, the applicant is referred to the rejections applied to claims 3 and 4 above.
Regarding claim 12, Lee in view of Bouche teaches the semiconductor device as recited in claim 8, wherein the gate cut is disposed between source/drain regions of the NFET and the PFET (Lee: Figs. 2, 4 and [0031], [0076]).
Regarding claim 13, Lee in view of Bouche teaches the semiconductor device as recited in claim 8, further comprising additional gate cuts disposed between source/drain regions having the same conductivity type (Lee: Figs. 15-16 and [0031], [0146]-[0147]).
Regarding claim 14, Lee in view of Bouche teaches the semiconductor device as recited in claim 8, wherein the first portion is coupled to the first backside power rail with a first local interconnect and the second portion is coupled to the second backside power rail with a second local interconnect (Bouche: Figs. 9-10 and [0111], [0125]).
Regarding claim 15, Lee in view of Bouche teaches the semiconductor device as recited in claim 14, wherein the first local interconnect and the second local interconnect are disposed within a layer for backside contacts (Bouche: Figs. 9-10 and [0111], [0125]).
Allowable Subject Matter
Claims 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claims 6 and 16, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a source/drain region connected to a top side contact is separated from the local interconnects by a backside interlevel dielectric layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
June 22, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
Prosecution Insights