DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-12 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al ( Yang, US 2020/0266286 A1).
Regarding claim 1, Yang shows a semiconductor device, comprising: a gate cut (gate cut in 100 in FIG. 1-9 and [0020]) disposed through a space between source/drain regions (source/drain region 150) and corresponding source/drain contacts (contacts 180 in FGI. 9 and [0031]), the gate cut having a top surface ( top surface 184) above a top surface of the source/drain contacts (contacts 180); and an asymmetric via ( opening 180 in FIG. 9) disposed on and wrapping around a side of a top portion of the gate cut ( gate cut 100) to connect one of the source/drain contacts (contacts 180) to a power rail ( element 110).
Regarding claim 2, Yang shows a semiconductor device, comprising, wherein the gate cut (gate cut 100) is disposed within a shallow trench isolation (STI 116).
Regarding claim 3, Yang shows a semiconductor device, further comprising a via ( opening 186 in FIG. 9) connected to the other one of the source/drain (source/drain 150) contacts at a position opposite the gate cut (gate cut 100).
Regarding claim 4, Yang shows a semiconductor device, further comprising the asymmetric via bar (contact 180) with an asymmetric cross-section via includes a via bar with an asymmetric cross-section (see FIG. 9).
Regarding claim 5, Yang shows a semiconductor device, further comprising, wherein the asymmetric via ( opening 186) is offset from a centerline of the power rail (element 110).
Regarding claim 8, Yang shows a semiconductor device, comprising: a first source/drain region (source/drain 150); a second source/drain region adjacent to the first source/drain region, the first source/drain region and second source/drain region having a space therebetween (source/drain region in FIG. 1 with respect to FIG. 9); a first contact (contact 180) connected to the first source/drain region (source/drain 150); a second contact (contact 180) connected to the second source/drain region (source/drain 150); a gate cut (gate cut 100) disposed through the space and extending between and above the first contact and the second contact (see FIG. 1 with respect to FIG. 9); and an asymmetric via (opening 186) disposed on and wrapping around a side of a top portion of the gate cut to connect the first contact to a power rail (see FIG. 1-9).
Regarding claim 9, Yang shows a semiconductor device, comprising, wherein the gate cut ( gate cut 100) is disposed within a shallow trench isolation (STI 116).
Regarding claim 10, Yang shows a semiconductor device, comprising, wherein a via (opening 186) connected to the second contact at a position opposite the gate cut (gate cut 100).
Regarding claim 11, Yang shows a semiconductor device, comprising, wherein the asymmetric via (opening 186) includes a via bar with an asymmetric cross-section (see FIG. 1 with respect to FIG. 9).
Regarding claim 12, Yang shows a semiconductor device, comprising, wherein the asymmetric via is offset from a centerline of the power rail (see FIG. 1 with respect to FIG. 9).
Regarding claim 15, Yang shows a method for fabrication of a semiconductor device, comprising: forming a gate cut (gate cut 100 in FIG. 9) through a space between source/drain regions (source/drain 150) and corresponding contacts to the source/drain regions; forming an asymmetric via (opening 186) disposed on and wrapping around a side of a top portion of the gate cut (cut 100); and connecting the asymmetric via to a power rail ( element 110), where the asymmetric via is offset from a centerline of the power rail.
Regarding claim 16, Yang shows a method for fabrication of a semiconductor device, wherein forming the gate cut includes: depositing additional dielectric material (element 182) to raise a height of the gate cut above the corresponding contacts (see FIG. 8).
Regarding claim 17, Yang shows a method for fabrication of a semiconductor device, wherein forming the gate cut includes forming the gate cut into a shallow trench isolation (STI 116).
Allowable Subject Matter
Claims 6-7 13-14 and 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
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