DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. Pub. 2014/0246731) [Hereafter “Chen”].
Regarding claims 1 and 18-20, Chen [Fig.11] discloses a semiconductor structure comprising:
a shallow trench isolation region [40’] comprising a first trench dielectric material having a first height; and
an active device region [66] located adjacent to the shallow trench isolation region and comprising a second trench dielectric material [40] having a second height, wherein the second height is less than the first height;
wherein the first trench dielectric material [40’] and the second trench dielectric material [40] are composed of a compositionally same trench dielectric material [Fig.5B];
further comprising a dielectric liner [34] located along sidewalls of the first trench dielectric material and along sidewalls of the second trench dielectric material [Figs.4-5];
wherein the first trench dielectric material [40’] is embedded in a semiconductor substrate [20].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-8 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Pub. 2014/0246731) in view of Cheng (U.S. Pat. 10410927).
Regarding claim 2, Chen fails to explicitly disclose wherein the shallow trench isolation region further comprises a first gate structure, and the active device region comprises a second gate structure. However, Cheng [Figs.1,15,18] discloses and makes obvious a semiconductor structure wherein the shallow trench isolation region [114] further comprises a first gate structure [904], and the active device region [104] comprises a second gate structure [902] [Fig.15]. Cheng [Col.1 lines 25-30] discloses the dummy gates over the trench isolation regions are needed for patterning purposes. It would have been obvious to provide the first and second gate structures as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 3-4, Cheng [Figs.1,15,18] discloses a semiconductor structure
wherein the first gate structure [904] has a smaller aspect ratio as compared to the second gate structure [902] [Gate structures 904 are wider];
wherein the first gate structure [904] is located entirely on the first trench dielectric material [114], and the second gate structure [902] is located on a surface of a semiconductor channel region [104] and a surface of the second trench dielectric material [“108” mislabeled in Fig.1 B-B xsection (probably should be labeled 114)] [Figs.1,15].
Regarding claims 16-17, Cheng [Figs.1,15,18] discloses a semiconductor structure
wherein the first gate structure [904] and the second gate structure [902] are both sacrificial gate structures [Figs.15-17];
wherein the first gate structure is an inactive functional gate structure [1802] and the second gate structure is a functional gate structure [1802] [Fig.18].
Regarding claims 5-6, Chen [Fig.11] discloses the semiconductor structure
wherein the semiconductor channel region comprises a semiconductor fin [42], and the first height of the first trench dielectric material [40’] is located between a topmost surface and a bottommost surface of the semiconductor fin;
wherein the second height of the second trench dielectric material [40] is located between the topmost surface and the bottommost surface of the semiconductor fin [42].
Regarding claims 7-8, Chen [Fig.11] and Cheng [Figs.1,15,18] disclose the semiconductor structure
wherein the semiconductor channel region [104] comprises a nanosheet stack [106], and the first height of the first trench dielectric material is located between a topmost surface and a bottommost surface of the nanosheet stack;
wherein the second height of the second trench dielectric material [“108”] is located beneath the bottommost surface of the nanosheet stack [106] [Cheng; Fig.1].
Chen discloses the heights of the trench dielectric materials and Cheng discloses the channel region comprising the nanosheet stack. It would have been obvious to include the channel region comprising the nanosheet stack into the structure of Chen, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Pub. 2014/0246731) in view of Cheng (U.S. Pat. 10410927), as applied above and further in view of Costrini et al. (U.S. Pub. 2016/0005735) [Hereafter “Costrini”].
Regarding claim 9, Chen fails to explicitly disclose wherein the first trench dielectric material has a middle portion having the first height and an end portion flanking each side of the middle portion having the second height. However, Costrini [Fig.14] discloses a semiconductor structure wherein the first trench dielectric material [22] has a middle portion [Fig.14B; region of 22 below 60] having the first height and an end portion flanking each side of the middle portion having the second height [recessed regions of 22].
It would have been obvious to provide the first trench dielectric material as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 10-11, Chen [Fig.11], Cheng [Figs.1,15,18], and Costrini [Fig.14] disclose the semiconductor structure
wherein the semiconductor channel region comprises a nanosheet stack, and the first height of the first trench dielectric material is located between a topmost surface and a bottommost surface of the nanosheet stack;
wherein the second height of both the first trench dielectric material and the second trench dielectric material is located beneath the bottommost surface of the nanosheet stack [Discussed above in the treatment of claims 7-8].
Regarding claims 12-15, Cheng [Figs.1,15,18] discloses
wherein the nanosheet stack [106] is located directly on a mesa portion [104] of a semiconductor substrate [Fig.1];
further comprising a sacrificial semiconductor base layer [108] located beneath the nanosheet stack [106] [Figs.1,16-17];
wherein the second height of both the first trench dielectric material [114] and the second trench dielectric material is located beneath a bottommost surface of the sacrificial semiconductor base layer [Figs.1,16-17];
wherein the sacrificial semiconductor base layer is located directly on a mesa portion [104] of a semiconductor substrate [Figs.1,16-17].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BAC H AU/Primary Examiner, Art Unit 2898