DETAILED ACTION
This correspondence is in response to the communications received December 7, 2023. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim is rendered indefinite due to the following italicized portions of the claims, “9. The trench FET device of claim 1, further comprising one or more parallel termination trenches extending along the first axis, wherein each of the parallel termination trenches comprises a single electrode with the same proportions as a combined structure of the gate electrode and the shield electrode.” It is unclear if the “one or more parallel termination trenches” are 1.) the same as claim 1’s “plurality of termination trenches”, or 2.) if the “one or more parallel termination trenches” are formed within each of the “plurality of termination trenches”, or 3.) if the “one or more parallel termination trenches” are not the same as and separated from the “plurality of termination trenches”. For purposes of examination, it will be assumed that since the second limitation introduces an electrode into the termination trenches, that the electrodes are in the “one or more parallel termination trenches” that are formed within each of the “plurality of termination trenches”.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1A, a trench field-effect transistor (FET) device comprising:
a plurality of active trenches (102) extending along a first axis (extending along vertical direction in Fig. 1A) and distributed along a second axis perpendicular to the first axis (plural 102 are distributed along horizontal direction in Fig. 1A), wherein each of the active trenches comprises a gate electrode (124) and a shield electrode (126); and
a plurality of termination trenches (108 and 110) extending along the second axis (direction along horizontal of Fig. 1A) and, arranged adjacent to the active trenches (next to 102), wherein each of the termination trenches is fully filled with a first dielectric material (¶ 0035),
wherein the shield electrode (126) is disposed to abut (A widely held definition of the term is, “next to, adjacent”) with a respective one of the termination trenches at each end of the shield electrode (“The vertical portion of the shield electrode 126 of each of the plurality of active trenches 102 is arranged to abut with a respective one of the two or more termination trenches 104 and 106 at each end. In an implementation, the vertical portion of the shield electrode 126 may also be referred to as an abutting termination trench.”, ¶ 0043).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 10, 13, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0043741) in view of Woo et al. (US 2023/0187537).
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Regarding claim 1, the prior art of Hu discloses in Figs. 4, 9 and 12, a trench field-effect transistor (FET) device (see title, “Termination for vertical trench shielded devices”, and “the vertical transistor can be a Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) 400”, ¶ 0037) comprising:
a plurality of active trenches (plural trenches that are filled with “gate regions 410 … gate shield regions 420” ¶ 0037, hereinafter referred to as ‘AT’) extending along a first axis (in Fig. 4, AT extend in direction from lower left to upper right direction, hereinafter referred to as ‘FA’) and distributed along a second axis (plural AT are distributed along horizontal direction, hereinafter referred to as ‘SA’) perpendicular to the first axis (SA perpendicular to FA),
wherein each of the active trenches comprises a gate electrode (“gate regions 410” ¶ 0037) and a shield electrode (“gate shield regions 420” ¶ 0037); and
a plurality of termination trenches (“one or more termination regions 445, and one or more termination insulator regions 450”, ¶ 0037, hereinafter referred to as ‘TT’, which arranged in a trench shape) extending along the second axis (portions of TT extend along SA perpendicularly crossing the AT) and, arranged adjacent to the active trenches (TT are ‘next to’ AT), wherein each of the termination trenches (TT) is fully filled with a first dielectric material (“one or more termination regions 445, and one or more termination insulator regions 450”, ¶ 0037),
wherein the shield electrode is disposed to abut with a respective one of the termination trenches at each end of the shield electrode (A widely held definition of the term is, “next to, adjacent”. As can be seen in Fig. 9 the vertical extension 420a of shield electrode 420 is ‘next to’ TT/455/450. The evidence that the termination trenches abut both ends of the device trenches with shield electrode therein, is that the termination trenches surround the device area, which includes the device trenches with shield electrode therein. “The termination region 450 and termination insulator region 455 can be disposed in a periphery region surrounding the core region that includes the one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425 and one or more body regions 430.”, ¶ 0039).
Hu teaches that the analogous termination trenches (“one or more termination regions 445, and one or more termination insulator regions 450”, ¶ 0037) are filled with “insulator” material, but does not explicitly disclose “dielectric” material. It is well known in the art that insulator material is a dielectric material.
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Woo discloses in Fig. 5, wherein a termination trench (trench formed in TR) abutting a device trench (“first trenches 33”, ¶ 0068) with shield electrode (“shield electrode 37”, ¶ 0068), wherein the termination trench is filled with dielectric material (“The dielectric area 36 has a pattern shape 361 at bottom of the dielectric area 36 and the pattern shape 361 corresponds to a bottom shape of the second trench.”, ¶ 0067).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“wherein each of the termination trenches is fully filled with a first dielectric material”, as disclosed by Woo in the system of Hu, for the purpose of preventing voltage breakdown or channel effect. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Hu et al. disclose the trench FET device of claim 1, wherein a first depth of the termination trenches is equal to or greater than a second depth of the active trenches (Hu discloses that termination trenches TT are equal depth to that of active trenches AT).
Regarding claim 3, the prior art of Hu et al. disclose the trench FET device of claim 1, further comprising at least one additional termination trench (two termination trenches are shown in Fig. 12) at each end of the active trenches (as disclosed in the rejection of claim 1, Hu shows where TT have regions positioned at both of the ends of AT) and arranged parallel to the termination trenches (the parallel arrangement of termination trenches TT and active trenches AT is shown in Fig. 12).
Regarding claim 10, the prior art of Hu discloses in Figs. 4, 9 and 12, a method of manufacturing a trench field-effect transistor (FET) device (see title, “Termination for vertical trench shielded devices”, and “the vertical transistor can be a Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) 400”, ¶ 0037) and comprising:
forming an epitaxial layer (“drift regions 435”, ¶ 0037, “the drift region can be formed by epitaxially depositing a moderately or lightly n-doped (N or N−) semiconductor, such as silicon doped with phosphorous or arsenic on the drain region”, ¶ 0054) on a substrate (interpreted to be “drain regions 440”, ¶ 0037);
(forming) a plurality of active trenches (plural trenches that are filled with “gate regions 410 … gate shield regions 420” ¶ 0037, hereinafter referred to as ‘AT’) … extending along a first axis (in Fig. 4, AT extend in direction from lower left to upper right direction, hereinafter referred to as ‘FA’) and distributed along a second axis (plural AT are distributed along horizontal direction, hereinafter referred to as ‘SA’) perpendicular to the first axis (SA perpendicular to FA) and to form a plurality of termination trenches (“one or more termination regions 445, and one or more termination insulator regions 450”, ¶ 0037, hereinafter referred to as ‘TT’, which arranged in a trench shape) extending along the second axis (portions of TT extend along SA perpendicularly crossing the AT) and arranged adjacent (A widely held definition of this term is, “next to, very near”) to the active trenches (As can be seen in Fig. 9 the vertical extension 420a of shield electrode 420 is ‘next to, very near’ TT/455/450. The evidence that the termination trenches abut both ends of the device trenches with shield electrode therein, is that the termination trenches surround the device area, which includes the device trenches with shield electrode therein. “The termination region 450 and termination insulator region 455 can be disposed in a periphery region surrounding the core region that includes the one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425 and one or more body regions 430.”, ¶ 0039);
fully filling the termination trenches (TT) with a first dielectric material (“one or more termination regions 445, and one or more termination insulator regions 450”, ¶ 0037, where the trench TT itself is filled as full as it can get, which is planar with surrounding upper surfaces);
forming a gate electrode (“gate regions 410”, ¶ 0037) in each of the active trenches (410 in AT);
forming a shield electrode (“gate shield regions 420”, ¶ 0038) disposed in each of the active trenches (420 in AT) to abut with a respective one of the termination trenches at each end of the shield electrode (A widely held definition of the term is, “next to, adjacent”. As can be seen in Fig. 9 the vertical extension 420a of shield electrode 420 is ‘next to’ TT/455/450. The evidence that the termination trenches abut both ends of the device trenches with shield electrode therein, is that the termination trenches surround the device area, which includes the device trenches with shield electrode therein. “The termination region 450 and termination insulator region 455 can be disposed in a periphery region surrounding the core region that includes the one or more source regions 405, one or more gate regions 410, one or more gate insulator regions 415, one or more gate shield regions 420, one or more gate shield insulator regions 425 and one or more body regions 430.”, ¶ 0039).
First, Hu does not disclose the etch process used to make the trenches for the embodiment of Fig. 4, and therefore does not disclose, “removing material from the epitaxial layer to form a plurality of active trenches”.
Hu does disclose, removing material from the epitaxial layer to form a plurality of active trenches (In method sequence of Fig. 17A, “trench mask and etching processes can be used to form gate and termination trenches”, ¶ 0056).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“removing material from the epitaxial layer to form a plurality of active trenches”, as disclosed by Fig. 17A of Hu in the system of Fig. 4 of Hu, for the purpose of creating trenches to form field generating electrodes so the transistor can be operated. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Hu does not explicitly disclose, “filling the termination trenches with a first dielectric material”. Hu teaches that the analogous termination trenches (“one or more termination regions 445, and one or more termination insulator regions 450”, ¶ 0037) are filled with “insulator” material, but does not explicitly disclose “dielectric” material. It is well known in the art that insulator material is a dielectric material.
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Woo discloses in Fig. 5, wherein a termination trench (trench formed in TR) abutting a device trench (“first trenches 33”, ¶ 0068) with shield electrode (“shield electrode 37”, ¶ 0068), wherein the termination trench is filled with dielectric material (“The dielectric area 36 has a pattern shape 361 at bottom of the dielectric area 36 and the pattern shape 361 corresponds to a bottom shape of the second trench.”, ¶ 0067).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“filling the termination trenches with a first dielectric material”, as disclosed by Woo in the system of Hu, for the purpose of preventing voltage breakdown or channel effect. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 13, the prior art of Hu et al. disclose the method of claim 10, and Hu discloses in Figs. 4, 9 and 12,
wherein forming the gate electrode (“gate region 410”, ¶ 0038) and the shield electrode (“gate shield region 420”, ¶ 0038) comprises:
depositing a first conductive material (420) into each of the active trenches (in AT);
depositing a second conductive material (410) into each of the active trenches (AT) to form the gate electrode (“gate region 410”, ¶ 0038) in each of the active trenches (in AT).
Hu fails to disclose, “partially removing the first conductive material to form the shield electrode in each of the active trenches”.
Woo teaches in Fig. 4A to 4B, where, partially removing the first conductive material to form the shield electrode in each of the active trenches (“The manufacturing process includes a deposition process to form a shield electrode 17 in the trench space 151. The shield electrode 17 includes a poly electrode. An anisotropy etching is conducted to the shield electrode 17. The shield electrode 17 at active region AR is further etched to create a space for forming a gate electrode.”, ¶ 0058).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“partially removing the first conductive material to form the shield electrode in each of the active trenches”, as disclosed by Nishiwaki in the system of Hu et al., for the purpose of preventing voltage breakdown or channel effect. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 19, the prior art of Hu et al. disclose the method of claim 13, and Woo discloses in Fig. 4A, wherein the first conductive material is polysilicon (“shield electrode 17 includes a poly electrode”, ¶ 0058).
Regarding claim 20, the prior art of Hu et al. disclose the method of claim 10, and Woo discloses in Fig. 4A, wherein the first dielectric material comprises a thick field oxide (in TR, “The dielectric area DA surrounds the active region AR to sustain the electric field in the termination region TR and reduce the process variation sensitivity of breakdown voltage.”, ¶ 0045, where 16 is an oxide, “the dielectric area 16 may be a fully oxidized trench area.”, ¶ 0050, thus a field and oxide which is relatively thick is present in TR).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0043741) in view of Woo et al. (US 2023/0187537) in view of Nishiwaki et al. (US 2019/0081173).
Regarding claim 9, the prior art of Hu et al. disclose the trench FET device of claim 1, however Hu fails to disclose, “further comprising one or more parallel termination trenches extending along the first axis (Hu shows the parallel termination trenches aspect in the rejection of claim 1, where TT has portion along FA, but does not show further trenches in the termination trenches where an electrode would reside), wherein each of the parallel termination trenches comprises a single electrode with the same proportions as a combined structure of the gate electrode and the shield electrode.”
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Nishiwaki discloses in Fig. 14, further comprising one or more parallel termination trenches extending along the first axis (trench formed in TT1, where electrode 42 resides, ¶ 0038, where Fig. 14 is stated to have same features as Fig. 4, ¶ 0098),
wherein each of the parallel termination trenches comprises a single electrode (42, ¶ 0038) with the same proportions as a combined structure of the gate electrode and the shield electrode (shown to have same proportions as “shield electrode” equivalent “field plate electrode 32” and “gate electrode 30”, ¶ 0099).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“further comprising one or more parallel termination trenches extending along the first axis, wherein each of the parallel termination trenches comprises a single electrode with the same proportions as a combined structure of the gate electrode and the shield electrode.”, as disclosed by Nishiwaki in the system of Hu et al., for the purpose of improving the breakdown voltage of the vertical transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0043741) in view of Woo et al. (US 2023/0187537) in view of Baliga (US 2005/0001268).
Regarding claim 14, the prior art of Hu et al. disclose the method of claim 13, and Nishiwaki discloses in Figs. 2C to 4E, further comprising:
depositing a dielectric layer to partially fill each of the active trenches before depositing the first conductive material (in Fig. 2C, “first dielectric layer 15”, ¶ 0050 is shown being deposited into active region trench 151, where Fig. 2C is the precursor in manufacturing sequence to Fig. 4A, ¶ 0057, which is before deposition of “shield electrode 17”, ¶ 0059); and
removing the first dielectric material (in etch step at Fig. 4A, top portions of both “shield electrode 17” and “first dielectric layer 15”, ¶ 0050, are removed by the step of Fig. 4B) and the first conductive material (“gate electrode 18”, ¶ 0060), after depositing the first conductive material (after formation of 17 in Fig. 4A).
Hu et al. do not disclose, “removing the first dielectric material and the first conductive material from an upper surface of the epitaxial layer to form a planar surface”.
Baliga discloses in Figs. 18C to 18E, where conductor 1210 and insulator 1208/1206 are initially over semiconductor region 1202, then partially removed to be flush with top of 1202.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“removing the first dielectric material and the first conductive material from an upper surface of the epitaxial layer to form a planar surface”, as disclosed by Baliga in the system of Hu et al., for the purpose disclosing the necessary steps to make the gate electrodes to allow for operation of the transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0043741) in view of Woo et al. (US 2023/0187537) in view of Baliga et al. (US 2005/0001268).
Regarding claim 16, the prior art of Hu et al. disclose the method of claim 13, and Woo discloses in Figs. 4A to 4C, further comprising:
partially filling each of the active trenches with the first dielectric material (in Fig. 4A, the left most trench is partially filled with 15); and
removing the first dielectric material … before depositing the second conductive material (in Fig. 4B, 15 is partially removed from left most trench, before the equivalent “second conductive material” 18 is deposited in the trench, as can be seen in Fig. 4C).
Woo does not disclose (italicized portion), “removing the first dielectric material from an upper surface of the epitaxial layer to form a planar surface before depositing the second conductive material.”
Baliga discloses in Figs. 18D to 18E, that a dielectric material (“thermal oxide layer 1206”, ¶ 0089) is patterned to be at a planar level with surrounding semiconductor surface (1202). So it is clear that one may pattern the lining dielectric to be at a level with the surrounding semiconductor material upper layer.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation, (italicized portion), “removing the first dielectric material from an upper surface of the epitaxial layer to form a planar surface before depositing the second conductive material”, as disclosed by Baliga in the system of Hu et al., for the purpose of protecting the semiconductor material at the upper portions of trench, while carrying out the formation steps to make the gate electrodes. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0043741) in view of Woo et al. (US 2023/0187537) in view of Baliga et al. (US 2005/0001268) in view of Marchant et al. (US 2007/0155104).
Regarding claim 17, the prior art of Hu et al. disclose the method of claim 16, however Hu does not disclose,
“further comprising:
depositing a first dielectric layer to fully fill each of the active trenches;
depositing and developing a mask to cover trenches other than the active trenches;
partially removing the first dielectric layer from the active trenches; and
removing the mask.”
Marchant discloses in Figs. 3B to 3E,
further comprising:
depositing a first dielectric layer (“dielectric layer 106”, ¶ 0042) to fully fill each of the active trenches (“active gate trenches 110A and 110B”, ¶ 0042, where these trenches are fully filled with 106 in Fig. 3B);
depositing and developing a mask (“mask 313” is deposited in Fig. 3D, Examiner takes ‘official notice’ on the “developing a mask”, as this aspect is a very well known concept in the art) to cover trenches other than the active trenches (“trench 112”, ¶ 0043, 112 is covered and active trenches 110A/B are not covered by mask);
partially removing the first dielectric layer from the active trenches (in step shown in Fig. 3D, 106 is partially removed in 110A/B); and
removing the mask (the mask is removed as evidenced by the lack of mask by step shown in Fig. 3E).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“further comprising:
depositing a first dielectric layer to fully fill each of the active trenches;
depositing and developing a mask to cover trenches other than the active trenches;
partially removing the first dielectric layer from the active trenches; and
removing the mask”, as disclosed by Marchant in the system of Hu et al., for the purpose of allowing for a different electrode configuration in the active trench versus the termination trench. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 18, the prior art of Hu et al. disclose the method of claim 17, and Marchant discloses, further comprising depositing a second dielectric layer (“dielectric layer 310”, ¶ 0044) to cover the upper surface (upper surface of 306A and 102) before depositing the second conductive material (310 is in place prior to the deposition of “polysilicon layer 120”, ¶ 0044, which then becomes “gate electrodes 130A”, ¶ 0045 in Figs. 3E-F).
Allowable Subject Matter
Claims 4-8, 11, 12 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 5-8 have been objected to due to their dependence upon claim 4. Claim 12 has been objected to due to its dependence upon claim 11.
“4. The trench FET device of claim 1, wherein one or more of the active trenches further comprises an end region extending beyond the respective one of the termination trenches and wherein each of the termination trenches is fully filled with a second dielectric material.”
“11. The method of claim 10, further comprising:
depositing a dielectric layer to fully fill each of the termination trenches and the active trenches;
depositing and developing a mask to cover the termination trenches;
removing the dielectric layer from the active trenches; and
removing the mask.”
An attempt to reject claim 15 under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0043741) in view of Woo et al. (US 2023/0187537) in view of Nishiwaki et al. (US 2019/0081173) in view of Baliga (US 2005/0001268), was attempted, however the specific step at the particular site of the termination trench and the specific sequence were not found in the prior art.
Regarding claim 15, the prior art of Hu et al. disclose the method of claim 13, further comprising removing the first dielectric material from the epitaxial layer to form one or more parallel termination trenches extending along the first axis (removal of epi drift layer of Hu clearly visible as the TT being present).
First, Hu does not further disclose, “wherein depositing the first conductive material comprises depositing the first conductive material into each of the one or more parallel termination trenches to form a single electrode with the same proportions as a combined structure of the gate electrode and the shield electrode”.
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Nishiwaki discloses in Fig. 14, wherein depositing the first conductive material comprises depositing the first conductive material into each of the one or more parallel termination trenches (depositing 42 into TT1) to form a single electrode with the same proportions as a combined structure of the gate electrode and the shield electrode (42 in TT1 has the same proportions as the gate electrode 30 and shield electrode equivalent 32 in active trench equivalent CT1, shown to have same proportions as “shield electrode” equivalent “field plate electrode 32” and “gate electrode 30”, ¶ 0099).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
“wherein depositing the first conductive material comprises depositing the first conductive material into each of the one or more parallel termination trenches to form a single electrode with the same proportions as a combined structure of the gate electrode and the shield electrode”, as disclosed by Nishiwaki in the system of Hu et al., for the purpose of improving the breakdown voltage of the vertical transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Hu et al. and Nishiwaki do not disclose the further limitations of,
“wherein the method further comprises:
depositing and developing a mask to cover the one or more parallel termination trenches before partially removing the first conductive material; and
removing the mask after partially removing the first conductive material.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893