DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 3/25/26 is acknowledged. The traversal is on the ground(s) that no serious burden exists in examination of both inventions. This is not found persuasive because different classification for the two claimed inventions is proof of serious burden in and of itself. As stated in MPEP 808.02, a serious burden is present when there is A) Separate classification thereof: this shows that each invention has attained recognition in the art as a separate subject for inventive effort, and also a separate field of search. Patents need not be cited to show separate classification.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhagavat et al US 2019/0326273.
Pertaining to claim 1, Bhagavat teaches a system on chip 115 comprising:
a processor 25; and
an input and output circuit 40/45 comprising a plurality of input and output elements 170 connected to the processor 25, wherein the plurality of input and output elements 170 comprises:
a first input and output element 170 spaced apart from the processor by a first distance; and
a second input and output element 170 spaced apart from the processor by a second distance, greater than the first distance, and connected to the processor by a first electrical path (through element 40) extending through a first region (arbitrary see Figure 4 marked up below) of the first input and output element, and
wherein the first input and output element 170 is connected to the processor by at least one first terminal provided in a second region (arbitrary) that is separate from the first region. See Figure 4 marked up below and note that the first and second regions can simply be different locations, which the elements thusly described are in different locations.
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Pertaining to claim 2, Bhagavat teaches the system on chip of claim 1, wherein the second input and output element comprises at least one second terminal provided in a portion adjacent to the first region See Figure 4 marked up below, and
wherein the second input and output element is connected to the processor by the first electrical path Layer 145, elements 170 and element 40 provide electrical pathways which extends from the processor, through the first region, toward the at least one second terminal. See Figure 4.
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Pertaining to claim 4, Bhagavat teaches the system on chip of claim 1, wherein the first region 145 of the first input and output element comprises a plurality of layers See Figure 4, and
wherein the second input and output element is connected to the processor by the first electrical path extending through a first layer, from among the plurality of layers of the first region Electrical connection is made among elements 150 in layer 145 across multiple layers as shown in Figure 4.
Pertaining to claim 7, Bhagavat teaches the system on chip of claim 1, wherein the first input and output element further comprises a first contact 225 see Figure 6 provided in the second region, and
wherein the first input and output element is configured to:
transmit a signal, received by the first contact, to the processor, using the at least one first terminal; and
output a signal, received by the at least one first terminal, using the first contact.
Statements of intended use (part in italics above) are not given any patentable weight. The device structure of Bhagavat is capable of performing the claim function, and the structure is the only element that has any patentable weight. If the structure is capable of carrying the signals, that is all that is required for rejection. See MPEP 2111.02 (II) Statements Reciting Purpose or Intended Use
Allowable Subject Matter
Claims 3, 5, 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 3, the prior art does not teach nor suggest wherein the plurality of input and output elements further comprises a third input and output element spaced apart from the processor by the first distance and provided to abut the first input and output element without a gap and a fourth input and output element spaced apart from the processor by the second distance and provided to abut the second input and output element and the third input and output element without a gap, wherein the fourth input and output element is connected to the processor by a second electrical path extending through a third region of the third input and output element.
With respect to claim 6, the prior art does not teach nor suggest wherein the power circuit has a width, equal to a width of the input and output circuit, and wherein the power circuit is adjacent to one surface of the second input and output element and adjacent to one surface of the fourth input and output element
With respect to claim 8, the prior art does not teach nor suggest wherein the at least one first terminal and the at least one second terminal are provided to be symmetrical with respect to a virtual reference line crossing a center of the first input and output element and a center of the second input and output element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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