CTNF 18/532,754 CTNF 82754 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-02 Applicant’s election of Species I: FIGS. 18A-18D in the reply filed on April 13, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). 08-06 AIA Claim s 10-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 13, 2026 . Information Disclosure Statement The information disclosure statement (IDS) submitted on December 7, 2023, March 17, 2025, and May 18, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings 06-36 AIA The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the frontside gate region in claims 1, 8, 9 and 18, dielectric isolation layer in claims 1, and 18, and a backside sacrificial placeholder in claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 1-9, 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1. Claim 1 recites the limitation “a frontside gate region” in the first line the of the claim language. Applicant’s originally filed specifications fail to explicitly disclose the structure nor what a frontside gate region encompasses. The frontside gate region was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art as to what the structure of a frontside gate region would encompass. Claims 2-9 are rejected for dependence upon a 112(a) rejected instance claim. Regarding claim 18. Claim 18 recites the limitation “a frontside gate region” in the first line the of the claim language. Claim 18 rejected for the same analogous reasons as claim 1 above. Claims 19-20 are rejected for dependence upon a 112(a) rejected instance claim. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-9, 18-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1. Claim 1 recites the limitation “a frontside gate region” in the first line the of the claim language. It is unclear to the examiner as to what structure is encompassed by a frontside gate region. For the purpose of examination and compact prosecution, examiner shall interpret “a frontside gate region” to be a gate stack layer as supported by applicant’s originally filed specification in [0127]. Claims 2-9 are rejected for dependence upon a 112(b) rejected instance claim. Regarding claim 18. Claim 18 recites the limitation “a frontside gate region” in the first line the of the claim language. Claim 18 rejected for the same analogous reasons as claim 1 above. Claims 19-20 are rejected for dependence upon a 112(b) rejected instance claim. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 6-9, and 18-20 are rejected under 35 U.S.C. 102( a)(1)/102(a)(2 ) as being anticipated by Huang (U.S. 2022/0310603) . Regarding claim 1. Huang discloses a semiconductor structure (FIG. 59A-59F), comprising: a backside gate extension (FIG. 59C, portion of item 1074 extending through dielectric item 1072) extending from a frontside gate region (FIG. 59C-59D, item 1070) through a dielectric isolation layer (FIG. 59C, item 1072); a backside gate contact (FIG. 59C, item 1233) partially disposed on the backside gate extension (FIG. 59C, item 1074); and a backside interconnect (FIG. 59C, item 1245) connected to the backside gate extension (FIG. 59C, item 1074) by the backside gate contact (FIG. 59C, item 1233). Regarding claim 2. Huang discloses all the limitations of the semiconductor structure according to claim 1 above. Huang further discloses further comprising a backside gate extension cap layer (FIG. 59C, item 1220) disposed on the backside gate extension (FIG. 59C, item 1074). Regarding claim 3. Huang discloses all the limitations of the semiconductor structure according to claim 2 above. Huang further discloses wherein the backside gate contact (FIG. 59C, item 1233) is further partially disposed on the backside gate extension cap layer (FIG. 59C, item 1220). Regarding claim 6. Huang discloses all the limitations of the semiconductor structure according to claim 1 above. Huang further discloses further comprising: a backside source/drain contact via (FIG. 59C, item 1012) connecting a backside source/drain contact (FIG. 59C, item 1050) to the backside interconnect (FIG. 59C, item 1245). Regarding claim 7. Huang discloses all the limitations of the semiconductor structure according to claim 6 above. Huang further discloses further comprising: a backside source/drain contact cap layer (FIG. 59C, item 1234) disposed on the backside source/drain contact (FIG. 59C, item 1050) and the backside source/drain contact via (FIG. 59C, item 1234). Regarding claim 8. Huang discloses all the limitations of the semiconductor structure according to claim 1 above. Huang further discloses wherein the frontside gate region (FIG. 59C-59D, item 1070) is disposed within a nanosheet (FIG. 59C-59D, item 1264) field-effect transistor ([0148]). Regarding claim 9. Huang discloses all the limitations of the semiconductor structure according to claim 8 above. Huang further discloses further comprising: a frontside metal gate contact (FIG. 59C, item 1120) connecting the frontside gate region (FIG. 59C, item 1070) to a frontside back-end-of-the line interconnect (FIG. 59C, item 1135). Regarding claim 18. Huang disclose an integrated circuit (FIG. 59A-59F), comprising: one or more semiconductor structures (FIG. 59A-59F), wherein at least one of the one or more semiconductor structures (FIG. 59A-59F) comprises: a backside gate extension (FIG. 59C, portion of item 1074 extending through dielectric item 1074) extending from a frontside gate region (FIG. 59C, item 1074) through a dielectric isolation layer (FIG. 59C, item 1072); a backside gate contact (FIG. 59C, item 1233) partially disposed on the backside gate extension (FIG. 59C, item 1074); and a backside interconnect (FIG. 59C, item 1245) connected to the backside gate extension (FIG. 59C, item 1074) by the backside gate contact (FIG. 59C, item 1233). Regarding claim 19. Huang discloses all the limitations of the semiconductor structure according to claim 18 above. Huang further discloses further comprising a backside gate extension cap layer (FIG. 59C, item 1220) disposed on the backside gate extension (FIG. 59C, item 1074). Regarding claim 20. Huang discloses all the limitations of the semiconductor structure according to claim 19 above. Huang further discloses wherein the backside gate contact (FIG. 59C, item 1233) is further partially disposed on the backside gate extension cap layer (FIG. 59C, item 1220) . 07-15 AIA Claim s 1, 4, and 5 are rejected under 35 U.S.C. 102( a)(1)/102(a)(2 ) as being anticipated by Huang (U.S. 2022/0310603) . Regarding claim 1. Huang discloses a semiconductor structure (FIG. 59A-59F), comprising: a backside gate extension (FIG. 59C, portion of item 1074 extending through dielectric item 1072) extending from a frontside gate region (FIG. 59C-59D, item 1070) through a dielectric isolation layer (FIG. 59C, item 1072); a backside gate contact (FIG. 59C, item 1120) partially disposed on the backside gate extension (FIG. 59C, item 1074); and a backside interconnect (FIG. 59C, item 1135) connected to the backside gate extension (FIG. 59C, item 1074) by the backside gate contact (FIG. 59C, item 1120). Regarding claim 4. Huang discloses all the limitations of the semiconductor structure according to claim 1 above. Huang further discloses further comprising: a first frontside source/drain region (FIG. 59A-59C, item 1050 on left side) and a second frontside source/drain region (FIG. 59A-59C, item 1050 on right side); a backside source/drain contact (FIG. 59A-59C, item 1090 on left side) disposed on the first frontside source/drain region (FIG. 59A-59C, item 1050 on left side); and a first backside source/drain contact cap layer (FIG. 59A-59C, item 1060 on left; [0163]) disposed on the backside source/drain contact (FIG. 59A-59C, item 1090 on left side). Regarding claim 5. Huang discloses all the limitations of the semiconductor structure according to claim 5 above. Huang further discloses further comprising: a backside sacrificial placeholder (FIG. 59A-59C, item 1090 on right side) disposed on the second frontside source/drain region (FIG. 59A-59C, item 1050 on right side); and a second backside source/drain contact cap layer (FIG. 59A-59C, item 1060 on right side; [0163]) disposed on the backside sacrificial placeholder (FIG. 59A-59C, item 1090 on right side) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Song et al (U.S. 2022/0093594) FIELD-EFFECT TRANSISTORS (FET) CIRCUITS EMPLOYING TOPSIDE AND BACKSIDE CONTACTS FOR TOPSIDE AND BACKSIDE ROUTING OF FET POWER AND LOGIC SIGNALS, AND RELATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.E.B./Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815 Application/Control Number: 18/532,754 Page 2 Art Unit: 2815 Application/Control Number: 18/532,754 Page 3 Art Unit: 2815 Application/Control Number: 18/532,754 Page 4 Art Unit: 2815 Application/Control Number: 18/532,754 Page 5 Art Unit: 2815 Application/Control Number: 18/532,754 Page 6 Art Unit: 2815 Application/Control Number: 18/532,754 Page 7 Art Unit: 2815 Application/Control Number: 18/532,754 Page 8 Art Unit: 2815 Application/Control Number: 18/532,754 Page 9 Art Unit: 2815 Application/Control Number: 18/532,754 Page 10 Art Unit: 2815
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