DETAILED ACTION
This Notice is responsive to communication filed on 01/26/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/02/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species 1, reading on Fig. 3A in the reply filed on 06/22/2026 is acknowledged.
Claims 14 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/22/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 13, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jahagirdar et al. (US 11,721,554).
Regarding claim 10, Jahagirdar discloses:
a semiconductor wafer Fig. 1c: 141 having a front side and a rear side,
wherein the front side is opposite the rear side,
the front side has different mechanical stress regions Fig. 1c: 151, 153,
a structured carrier substrate Fig. 1c: 145 that has different materials with different material properties is arranged on the front side,
wherein the different materials are arranged on the different mechanical stress regions (col. 10: lines 6-22; i.e. first material at location 152 and overlapping region 151, and second material at location 154 overlapping region 153).
Regarding claim 13, Jahagirdar discloses the semiconductor wafer according to claim 10, wherein the different materials (i.e. first and second materials at locations Fig. 1c: 152, 154) are arranged alternately relative to one another above certain of the mechanical stress regions (i.e. regions 151 and 153) vertically with respect to the front side (shown in Fig. 1c).
Regarding claim 17, Jahagirdar discloses the semiconductor wafer according to claim 10, wherein the semiconductor wafer Fig. 1c: 141 includes silicon, or silicon carbide, or sapphire, or gallium nitride, or QST (col. 4, lines 54-56).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. (US 11,721,554) as applied to claim 10 above, and further in view of Yamaguchi et al. (US 6,610,934).
Regarding claim 16, Yamaguchi discloses the following limitations not disclosed by Jahagirdar:
the semiconductor wafer according to claim 10, wherein the different materials are printed (col. 16, lines 50-56).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Jahagirdar’s teachings with Yamaguchi’s teachings in order to relieve the stress exerting on the external connection terminal more efficiently (col. 16, lines 54-65).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jahagirdar et al. (US 11,721,554), and further in view of Yamaguchi et al. (US 6,610,934) and Zhao et al. (US 20150380339).
Regarding claim 18, Jahagirdar discloses the following claim limitations:
a method for processing a semiconductor wafer, wherein the semiconductor wafer has a front side and a rear side, wherein the front side is opposite the rear side, the method comprising the following steps:
ascertaining different mechanical stress regions Fig. 1c: 151, 153 on the front side of the semiconductor wafer Fig. 1c: 141 (col. 9, lines 59-65);
generating a structured carrier substrate Fig. 1c: 145 on the front side of the semiconductor wafer Fig. 1c: 141,
wherein different materials with different material properties are applied to the different mechanical stress regions (col. 10: lines 6-22; i.e. first material at location 152 and overlapping region 151, and second material at location 154 overlapping region 153) using printing methods;
grinding the rear side of the semiconductor wafer to a certain thickness Fig. 4: 407 (col. 11, lines 19-22 teaches the stress compensation layer remains on a different side than a grinding of the device);
dividing the semiconductor wafer; and
detaching the structured carrier substrate from the front side of the semiconductor wafer.
Yamaguchi et al teach the following limitations not disclosed by Jahagirdar:
using printing methods
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Jahagirdar’s teachings with Yamaguchi’s teachings in order to relieve the stress exerting on the external connection terminal more efficiently (col. 16, lines 54-65).
Zhao et al teach the following limitations not disclosed by Jahagirdar:
dividing the semiconductor wafer Fig. 3k: 124 (para. 0021 “cutting or singulating the finished wafer); and
detaching the structured carrier substrate Fig. 3i: 150 from the front side of the semiconductor wafer Fig. 3i: 124 (para. 0049).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Jahagirdar with Zhao in order to expose the active surface of the semiconductor die and conductive vias (para. 0049) and to allow the individual semiconductor die be inspected and electrically tested for identification of KGD post singulation (para. 0050).
Allowable Subject Matter
Claim11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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