DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-12 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. 2022/0102236; hereinafter “Kim”).
Regarding Claim 1, Kim discloses a package comprising: a first substrate 160 (page 3, paragraph 39); an integrated device (120, 130, 140, 150) (page 2, paragraph 25) coupled to the first substrate 160 (see fig. 1A), wherein the integrated device (120, 130, 140, 150) comprises a step back side (the integrated device has a stepped shape defined by a first length S1 and a second length S2; see figs. 1A, 3A and 3B); a second substrate (110, 190) comprising a cavity 112 (page 2, paragraph 26), wherein the integrated device (120, 130, 140, 150) is located at least partially in the cavity 112 of the second substrate (110, 190) (see fig. 1A); and an encapsulation layer 180 (page 4, paragraph 42) coupled to the first substrate 160 and the second substrate (110, 190) (see fig. 1A), wherein the encapsulation layer 180 is located between the first substrate 160 and the second substrate (110, 190) (see fig. 1A), and wherein the encapsulation layer 180 is located at least partially in the cavity 112 of the second substrate (110, 190) (see fig. 1A).
Regarding Claim 2, Kim discloses wherein the integrated device (120, 130, 140, 150) comprises a die substrate (130, 140, 150) (the integrated device includes a die substrate disposed on a semiconductor chip 120, the die substrate comprising an adhesive layer 130, a thin film layer 140, and a heat spreader layer 150) that includes a step contour (see figs. 3A and 3B).
Regarding Claim 3, Kim discloses wherein the die substrate (130, 140, 150) comprises a first thickness H1 and a second thickness (H2 + H3) that is different from the first thickness H1 (H1 and H3 may have the same thickness; page 3, paragraph 38).
Regarding Claim 4, Kim discloses wherein a first portion 130 of the die substrate (130, 140, 150) comprises a first width (W1, W2), and wherein a second portion (140, 150) of the die substrate (130, 140, 150) comprises a second width (W3-W6) that is different from the first width (W1, W2) (the second width W3-W6 is less than the first width W1, W2; see figs. 3A and 3B).
Regarding Claim 9, Kim discloses wherein the first substrate 160 comprises: at least one first dielectric layer 162 (page 3, paragraph 39); and a first plurality of interconnects (164, 166) (page 3, paragraph 39), and wherein the second substrate (110, 190) comprises: at least one second dielectric layer (114, 192) (page 2, paragraph 30; page 4, paragraph 44); and a second plurality of interconnects (116, 118, 194, 196, 198, 199) (page 2, paragraph 26; page 4, paragraphs 44 and 46).
Regarding Claim 10, Kim discloses wherein the second plurality of interconnects (116, 118, 194, 196, 198, 199) of the second substrate (110, 190) comprise a plurality of trace interconnects 116 (page 2, paragraph 26) that are located laterally to the integrated device (120, 130, 140, 150) (see fig. 1A).
Regarding Claim 11, Kim discloses wherein the second plurality of interconnects (116, 118, 194, 196, 198, 199) of the second substrate (110, 190) comprise a plurality of trace interconnects (116, 198) (page 2, paragraph 26) that are (i) located laterally to the integrated device (120, 130, 140, 150) (see fig. 1A) and (ii) vertically overlap with a portion of the integrated device (120, 130, 140, 150) (see fig. 1A).
Regarding Claim 12, Kim discloses further comprising a second integrated device 520 (page 6, paragraph 63) coupled to the second substrate (110, 190) through at least a plurality of solder interconnects (page 4, paragraph 41; see fig. 11).
Regarding Claim 15, Kim discloses a method for fabricating a package comprising: providing a first substrate 160 (page 3, paragraph 39); coupling an integrated device (120, 130, 140, 150) (page 2, paragraph 25) to the first substrate 160 (see fig. 1A), wherein the integrated device (120, 130, 140, 150) comprises a step back side (the integrated device has a stepped shape defined by a first length S1 and a second length S2; see figs. 1A, 3A and 3B); proving a second substrate (110, 190) comprising a cavity 112 (page 2, paragraph 26), wherein the second substrate (110, 190) is provided such that the integrated device (120, 130, 140, 150) is located at least partially in the cavity 112 of the second substrate (110, 190) (see fig. 1A); and forming an encapsulation layer 180 (page 4, paragraph 42) that is coupled to the first substrate 160 and the second substrate (110, 190) (see fig. 1A), wherein the encapsulation layer 180 is located between the first substrate 160 and the second substrate (110, 190) (see fig. 1A), and wherein the encapsulation layer 180 is located at least partially in the cavity 112 of the second substrate (110, 190) (see fig. 1A).
Regarding Claim 16, Kim discloses wherein the integrated device (120, 130, 140, 150) comprises a die substrate (130, 140) (the integrated device includes a die substrate disposed on a semiconductor chip 120, the die substrate comprising an adhesive layer 130 and a thin film layer 140) that includes a step contour (see figs. 3A and 3B).
Regarding Claim 17, Kim discloses wherein the die substrate (130, 140) comprises a first thickness H1 and a second thickness H2 that is different from the first thickness H1 (page 3, paragraphs 34 and 37; see figs. 3A and 3B).
Regarding Claim 4, Kim discloses wherein a first portion 130 of the die substrate (130, 140) comprises a first width (W1, W2), and wherein a second portion 140 of the die substrate (130, 140) comprises a second width (W3, W4) that is different from the first width (W1, W2) (the second width W3, W4 is less than the first width W1, W2; page 3, paragraph 36; see figs. 3A and 3B).
Regarding Claim 19, Kim discloses further comprising a second die substrate 150 (because a heat spreader layer 150 is disposed on and mechanically supports the semiconductor chip 120, it may be considered a die substrate) coupled to the die substrate (130, 140) (see figs. 1A, 3A and 3B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Im et al. (US Pub. 2018/0315740; hereinafter “Im”).
Regarding Claim 8, Kim fails to disclose explicitly wherein the cavity has a cavity width that is less than a width of the integrated device.
However, Im discloses wherein an interposer 300, considered as a substrate, may include an interposer hole 300h-_1 (page 2, paragraph 27), wherein the interposer hole 300h_1 width is less than a width W1 of a first semiconductor chip 110 (see fig. 2A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a cavity of a substrate having a width less than a width of an integrated device, as taught by Im, in order to accommodate the integrated device while maintaining structural support around its periphery.
Regarding Claim 13, Kim fails to disclose explicitly wherein the integrated device is coupled to the first substrate through at least one a plurality of solder interconnects.
However, Im discloses wherein a first semiconductor chip 110 is connected to a first semiconductor package substrate 101 through a plurality of solder balls 113 (pages 1-2, paragraph 15; see fig. 2A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to couple an integrated device and a substrate through a plurality of solder interconnects, as taught by Im, in order to provide reliable electrical and mechanical connection while accommodating thermal expansion differences between the integrated device and the substrate.
Allowable Subject Matter
Claims 5-7, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 recites a second die substrate coupled to the die substrate through an adhesive.
Claim 6 recites a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate, wherein the plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate.
Claim 14 recites the integrated device is coupled to the first substrate through at least a plurality of solder interconnects and a plurality of pillar interconnects.
Claim 20 recites the second substrate is coupled to the first substrate through a plurality of ball interconnects and a plurality of solder interconnects, and wherein the plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claim 7 depends from claim 6, so it is objected for the same reason.
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 February 6, 2026