Prosecution Insights
Last updated: April 19, 2026
Application No. 18/532,865

Thin Film Transistor and Display Device

Non-Final OA §103
Filed
Dec 07, 2023
Examiner
KIM, SU C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
65%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
695 granted / 899 resolved
+9.3% vs TC avg
Minimal -12% lift
Without
With
+-12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
48 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§103
57.6%
+17.6% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 899 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 9671646) in view of Hu (US 20170186783). Regarding claim 1, Tang discloses that a thin film transistor comprising: a substrate 10 (Fig. 8); a main light shield layer 20 located on the substrate 10; a first buffer layer 23 located on the main light shield layer 20; an active layer 30 located on the first buffer layer 23 and comprising a channel area, a first area 31 located on one side of the channel area, and a second area 31 (on other side) located on another side of the channel area, wherein the first area comprises a first main conductorized portion (heavily dopped) and a first induced conductorized portion 33 (lightly dopped, and the second area comprises a second main conductorized portion 31 and a second induced conductorized portion 33 (Fig. 8); a gate insulator layer 50 located on the active layer 30; a main source electrode 61/62 located on the gate insulator layer 50 and electrically connected to the first main conductorized portion (Fig. 8); a main drain electrode 62/61 located on the gate insulator layer 50 and electrically connected to the second main conductorized portion 31 (Fig. 8); and a gate electrode 51 located on the gate insulator layer 50 and overlapping the channel area 30, wherein the first induced conductorized portion 33 is located between the first main conductorized portion 31 and the channel area 32, and overlaps a portion of one side of the main light shield layer 20, and the second induced conductorized portion 33 is located between the second main conductorized portion 62/61 and the channel area 32, and overlaps a portion of another side of the main light shield layer 20 (Fig. 8). Tang fails to specify that the first induced conductorized portion does not overlap the main source electrode and the second induced conductorized portion does not overlap the main drain electrode. However, Hu suggest that the first induced conductorized portion 41 does not overlap the main source electrode 82/83 and the second induced conductorized portion 41 does not overlap the main drain electrode 83/82 (Fig. 18). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Tang with the first induced conductorized portion does not overlap the main source electrode and the second induced conductorized portion does not overlap the main drain electrode as taught by Hu in order to low leakage current and improved reliability (para. 0091) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Reclaim 2, Tang & Hu disclose that the main light shield layer is electrically connected to one of the gate electrode, the main source electrode, or the main drain electrode (Hu, para. 0014) Reclaim 3, Tang & Hu disclose that the main light shield layer comprises a first main light shield layer 21 and a second main light shield layer 21, the first main light shield layer overlaps the first induced conductorized portion 41, the second main light shield layer 21 overlaps the second induced conductorized portion 41, and the first main light shield layer and the second main light shield layer are spaced apart from each other (Hu Fig. 18). Reclaim 4, Tang & Hu disclose that a sub- source electrode located on the first main conductorized portion and a sub-drain electrode located on the second main conductorized portion, wherein the sub-source electrode is a reactive metal layer that reduces the first main conductorized portion, and the sub-drain electrode is a reactive metal layer that reduces the second main conductorized portion (Fig. 8, Tang). Reclaim 5, Tang & Hu disclose that a second buffer layer (a buffer can be mutli-layers. , Tang & Hu disclose that, Hu para. 0079, note: combination) located on the main light shield layer 21; and a sub-light shield layer 21 located on the second buffer layer and overlapping the main light shield layer, wherein the first induced conductorized portion overlaps a portion of one side of the sub-light shield layer, and the second induced conductorized portion overlaps a portion of another side of the sub-light shield layer (Hu, Fig. 18). Reclaim 6, Tang & Hu disclose that the sub-light shield layer is electrically connected to one of the gate electrode, the main source electrode, or the main drain electrode (Hu, Fig. 18. Para. 0014). Reclaim 7, Tang & Hu disclose that the sub-light shield layer 21 comprises a first sub-light shield layer and a second sub-light shield layer, wherein the first sub-light shield layer overlaps the first induced conductorized portion, the second sub-light shield layer overlaps the second induced conductorized portion, and the first sub-light shield layer and the second sub-light shield layer are spaced apart from each other (Fig. 18). Reclaim 8, Tang & Hu disclose that the main light shield layer comprises a first main light shield layer and a second main light shield layer, wherein the first main light shield layer overlaps the first induced conductorized portion and the first sub-light shield layer, the second main light shield layer overlaps the second induced conductorized portion and the second sub-light shield layer, and the first main light shield layer and the second main light shield layer are spaced apart from each other (Fig. 18). Reclaim 9, Tang & Hu disclose that at least one of the main light shield layer and the sub-light shield layer is electrically connected to one of the gate electrode, the main source electrode, or the main drain electrode (Fig. 18). Reclaim 10, Tang & Hu disclose that each of the gate electrode, the main source electrode, and the main drain electrode comprises at least one material selected from a group consisting of Ag, Al, Mg, Cr, Ti, Ni, W, Au, Ta, Nd, Cu, Co, Fe, Mo, Pt, and alloys thereof (Hu, para. 0090). Reclaim 11, Tang & Hu disclose that the gate electrode, the main source electrode, and the main drain electrode comprise a same material (Fig. 18, Hu, para. 0090). Reclaim 12, Tang & Hu disclose that the gate electrode comprises a different material from the main source electrode and the main drain electrode (Hu, para. 0090, can be different). Reclaim 13, Tang & Hu disclose that each of the sub- source electrode and the sub-drain electrode comprises at least one material selected from a group consisting of Al, Ti, Mo, and alloys thereof (Tang, col. 4, lines 46-48). Reclaim 14, Tang & Hu disclose that a specific resistance of the main light shield layer is lower than the specific resistance of the sub-light shield layer (Tang, Col. 4, lines 46-48). Reclaim 15, Tang & Hu disclose that the main light shield layer comprises at least one material selected from a group consisting of Ag, Al, Mo, Cu, and alloys thereof, and the sub-light shield layer comprises at least one material selected from a group consisting of In, Sn, and Zn (Tang, col. 4, lines 46-48). Reclaim 16, Tang & Hu disclose that a passivation layer located on the gate electrode, the main source electrode is located on the passivation layer and electrically connected to the first main conductorized portion, and the main drain electrode is located on the passivation layer and electrically connected to the second main conductorized portion (Tang, Fig. 18). Regarding claim 17, Tang & Hu disclose that a display device comprising a substrate 10 on which a plurality of thin film transistors are disposed, wherein at least one of the plurality of thin film transistors comprises: a main light shield layer 20 located on the substrate 10 (Fig. 8); a first buffer layer 23 located on the main light shield layer; an active layer 30 located on the first buffer layer 23 and comprising a channel area, a first area 31 located on one side of the channel area, and a second area 31 located on another side of the channel area, wherein the first area comprises a first main conductorized 31 portion and a first induced conductorized portion 33 , and the second area comprises a second main conductorized portion 31 and a second induced conductorized portion 33 (Tang, Fig. 8); a gate insulator layer 50 that is located on the active layer 30; a main source electrode 61/62 that is located on the gate insulator layer 50 and that is electrically connected to the first main conductorized portion 31; a main drain electrode 62/61 that is located on the gate insulator layer 50 and that is electrically connected to the second main conductorized portion 31 (Fig. 8); and a gate electrode 51 that is located on the gate insulator layer 50 and that overlaps the channel area 30, wherein the first induced conductorized portion 42 is located between the first main conductorized portion 41 and the channel area 41 (Hu, Fig. 18), does not overlap the main source electrode 82/83 (Hu, Fig. 18), and overlaps a portion of one side of the main light shield layer 21 , and the second induced conductorized portion 42 is located between the second main 40 conductorized portion and the channel area 41 (at center), does not overlap the main drain electrode 83/82, and overlaps a portion of another side of the main light shield layer (Fig. 18). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 07, 2023
Application Filed
Mar 03, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
65%
With Interview (-12.4%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 899 resolved cases by this examiner. Grant probability derived from career allow rate.

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