Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Athreya at fig. 6-8 discloses all the limitations of claim 1.
Drawings
To expedite the process of the prosecution, the examiner assumes element 210 as top-left corner or “A1 corner” of the socket and element 230 as top-left corner (A1 corner) of chip package.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 6-11, 13-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Athreya et al. (US 2016/0254629 A1), hereafter Athreya.
Regarding claim 1, Athreya at fig. 6-9 and ¶0048-0056 discloses a socket apparatus 600, comprising: a socket cavity sized and configured to receive a chip package [cavity for 106 as shown at fig. 6b]; a plurality of base contacts portion of 608/208/408 near 210] on a bottom surface S2 of the socket a socket housing 604/204/504, the plurality of base contacts being mountable on a circuit board 102; and a plurality of uniformly oriented pins [top portion of 608 under 106 as shown at fig. 8a,8b similar to 211,209] positioned across a top surface [S1 as an example] of the socket apparatus housing opposite the bottom surface, each pin of the plurality of uniformly oriented pins [uniform as shown at fig. 3] having a location that is referenced relative to a datum reference [top right sides corner of 204 at fig. 3 where curve portion of 211,209 faces], wherein the datum reference is positioned in a first corner of the socket housing [top right corner of 204 at fig. 3], wherein the plurality of uniformly oriented pins deflect in a uniform direction and parallel to one another [see fig. 3 and 8a, 8b], and wherein, when a load from the chip package 106 is applied to the plurality of uniformly oriented pins [see fig. 3, 8a, 8b], the plurality of uniformly oriented pins flex to apply a biasing force toward a first corner of the chip package [when 106 is loaded. See fig. 8a, 8b], the biasing force oriented to the first corner of the socket housing [implicit to orientation of 608 of 604 when 106 compressed], wherein a top portion [top of curved/angle portion of 608 near 106a] of each uniformly oriented pin of the plurality of uniformly oriented pins is angled [see curved/angled portion of 608/211,209] in parallel to a diagonal of the socket cavity extending from the first corner of the socket housing [fig. 3, 8a, 8b] and parallel to biasing force [due to orientation of 608 under pressure], wherein an angling of the top portion is parallel to the diagonal of the socket cavity [see fig. 3, 8a, 8b] and causes each uniformly oriented pin of the plurality of uniformly oriented pins to flex in the uniform direction when the load is applied [fig. 8a, 8b], wherein the uniform direction is parallel to the diagonal towards the first corner [fig. 3], and wherein, when a plurality of electrical pads 106a of the chip package 106 come into contact with the plurality of uniformly oriented pins and the load is applied [fig. 8b], the plurality of uniformly oriented pins are configured to wipe along the plurality of base contacts in the uniform direction [wiping direction of plurality of 608 towards corner as shown from fig. 3-*b] towards the first corner of the socket housing [wiping direction of 608 towards corner as shown from fig. 8a, 8b].
2. (Canceled).
Regarding claim 3, Athreya at fig. 6-8 discloses the socket apparatus of claim 1, wherein the plurality of uniformly oriented pins [608 as an example similar to 408a] is configured to wipe between initial contact points [initial contact before compressive force] and final resting points [fig. 8a, 8b] in which a direction between the initial contact points and the final resting points is towards the first corner of the socket housing parallel to a diagonal of the socket cavity [wiping direction of 608 towards the corner as shown from fig. 8a-8b and 3]. .
Regarding claim 4, Athreya at fig. 6-8 discloses the socket apparatus of claim 3, each initial contact point and each final resting point of the plurality of uniformly oriented pins are within an area of a corresponding electrical pad from the plurality of electrical pads [wiping area of pad 106a of plurality of 106a].
5. (Canceled).
Regarding claim 6, Athreya at fig. 6-8 discloses the socket apparatus of claim 1, wherein the socket cavity includes one or more of: a partial enclosure [partial enclosures as shown at fig. 6-8 on top surface of 604 similar to 562] of the top surface of the socket housing, the partial enclosure including at least a corner structure [four corner as shown at shown at fig. 6] around the first corner of the socket housing [corner alignment feature similar to 562]; or a full enclosure of the socket housing.
Regarding claim 7, Athreya at fig. 8a-8b discloses the socket apparatus of claim 1, wherein the plurality of base contacts and the plurality of uniformly oriented pins are part of a continuous member 608 having solder balls 210 added to the plurality of base contacts to solder the continuous member to the circuit board 102.
Regarding claim 8, Athreya at fig. 6-8 and ¶0047-0048 discloses the socket apparatus of claim 1, wherein the socket apparatus housing has a first size, and wherein the chip package has a second size having a set of dimensions that are smaller than the first size such that the chip package fits within the socket cavity of the socket housing.
Regarding claim 9, Athreya at fig. 6-8 and ¶0047-0048 discloses the socket apparatus of claim 1, wherein the socket housing includes a ball grid array (BGA) [because of 210].
Regarding claim 10, Athreya at fig. 6-8 discloses the socket apparatus of claim 1, wherein the chip package is a land grid array (LGA) package [106a of 106 is land].
Regarding claim 11, Athreya at rejection of claim 1 above and at fig. 8a-8b discloses the circuit board package, comprising: a circuit board 102; and a socket apparatus mounted to the circuit board via a plurality of base contacts on a bottom surface of a socket housing 604/204/504 of the socket apparatus, the socket apparatus comprising: a socket cavity sized and configured to receive a chip package; and a plurality of uniformly oriented pins positioned across a top surface of the socket apparatus housing opposite the bottom surface, each pin of the plurality of uniformly oriented pins having a location that is referenced relative to a datum reference, wherein the datum reference is positioned in a first corner of the socket housing, wherein the plurality of uniformly oriented pins deflect in a uniform direction and parallel to one another, and wherein, when a load from the chip package is applied to the plurality of uniformly oriented pins, the plurality of uniformly oriented pins flex to apply a biasing force toward a first corner of the chip package, the biasing force oriented to the first corner of the socket housing, wherein a top portion of each uniformly oriented pin of the plurality of uniformly oriented pins is angled in parallel to a diagonal of the socket cavity extending from the first corner of the socket housing and parallel to biasing force, wherein an angling of the top portion is parallel to the diagonal of the socket cavity and causes each uniformly oriented pin of the plurality of uniformly oriented pins to flex in the uniform direction when the load is applied, wherein the uniform direction is parallel to the diagonal towards the first corner, and wherein, when a plurality of electrical pads of the chip package come into contact with the plurality of uniformly oriented pins and the load is applied, the plurality of uniformly oriented pins are configured to wipe along the plurality of base contacts in the uniform direction towards the first corner of the socket housing.
12. (Canceled).
Regarding claim 13, Athreya at rejection of claim 4 above and at fig. 8a-8b discloses the circuit board package of claim 11, wherein each electrical pad 106a of the plurality of electrical pads of the chip package has a pad location [location of 106a] that is referenced relative to the datum reference, wherein the datum reference is positioned in the first corner of the chip package that aligns with the first corner of the socket housing when the chip package is placed within the socket cavity [corner of 106 when loaded with corner (datum reference corner) of 604/204/504].
Regarding claim 14, Athreya at rejection of claim 4 above and at fig. 8a-8b discloses the circuit board package of claim 11, wherein the first corner of the chip package and the first corner of the socket apparatus housing is a same physical corner [corner of 106 when loaded with corner (datum reference corner) of 604/204/504].
Regarding claim 15, Athreya at rejection of claim 9-10 above and at fig. 8a-8b discloses the circuit board package of claim 11, wherein the chip package is a land grid array (LGA) package, and wherein the socket apparatus housing includes a ball grid array (BGA).
Regarding claim 16, Athreya at rejection of claim 3 above and at fig. 8a-8b discloses the circuit board package of claim 11, wherein the plurality of uniformly oriented pins is configured to wipe between an initial contact point and a final resting point in which a direction between the initial contact point and the final resting point is parallel to a diagonal of the socket cavity passing through and toward the first corner of the socket housing.
Regarding claim 17, Athreya at rejection of claims 1 and 11 above and at fig. 8a-8b discloses the method of facilitating an electrical connection between a circuit board and a chip package, comprising: mounting a socket apparatus to the circuit board via a plurality of base contacts on a bottom surface of a socket housing of the socket apparatus, the socket apparatus including a plurality of uniformly oriented pins positioned across a top surface of the socket apparatus housing opposite the bottom surface, each uniformly oriented pin of the plurality of uniformly oriented pins having a location that is referenced relative to a datum reference, wherein the datum reference is positioned in a first corner of the socket housing, wherein the plurality of uniformly oriented pins deflect in a uniform direction and parallel to one another, and wherein, when a load from the chip package is applied to the plurality of uniformly oriented pins, the plurality of uniformly oriented pins flex to apply a biasing force toward a first corner of the chip package, the biasing force oriented to the first corner of the socket housing, wherein a top portion of each uniformly oriented pin of the plurality of uniformly oriented pins is angled in parallel to a diagonal of a socket cavity of the socket apparatus, the diagonal extending from the first corner of the socket housing, wherein an angling of the top portion is parallel to the diagonal of the socket cavity and causes each uniformly oriented pin of the plurality of uniformly oriented pins to flex in the uniform direction when the load is applied, wherein the uniform direction is parallel to the diagonal towards the first corner, and wherein, when a plurality of electrical pads of the chip package come into contact with the plurality of uniformly oriented pins and the load is applied, the plurality of uniformly oriented pins are configured to wipe along the plurality of base contacts in the uniform direction towards the first corner of the socket housing; placing the chip package 106 within a socket cavity [fig. 5, 8] of the socket apparatus housing to position a plurality of electrical pads 106a on the chip package in contact with the plurality of uniformly oriented pins 608/408a on the top surface of the socket housing; and applying a biasing load [compressive force as explained] to the chip package in the uniform direction such that a first corner of the chip package is biased to the first corner of the socket housing.
18. (Canceled).
Regarding claim 19, Athreya at rejection of claims 1 and 11 above and at fig. 8a-8b discloses the method of claim 17, wherein the biasing load is caused by a combination of physical placement of the chip package [compressive force as shown and fig. 8b] in the first corner of the socket apparatus housing and wiping of the plurality of uniformly oriented pins in parallel to a diagonal of the socket cavity passing through and towards the first corner of the socket housing [compressive force as explained and fig. 5, 8].
Regarding claim 20, Athreya at rejection of claims 3 and 16 above and at fig. 8a-8b discloses the method of claim 17, wherein the plurality of uniformly oriented pins are configured to wipe between an initial contact point and a final resting point in which a direction between the initial contact point and the final resting point is parallel to a diagonal of the socket cavity passing through and towards the first corner of the socket housing.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PARESH PATEL/Primary Examiner, Art Unit 2858
June 12, 2026
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