DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the first substrate component or the second substrate component" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 8-12, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Wang et al (U.S. Pub #2022/0352137).
With respect to claim 1, Wang teaches a semiconductor package, comprising:
a first chip (Fig. 2, 105a and Paragraph 53) having a first surface, and a second surface (Fig. 2, bottom surface) opposite the first surface;
a chip interconnect component (Fig. 2, 110+140) on the second surface of the first chip; and
a second chip (Fig. 2, 105c) on the chip interconnect component, the second chip including a third surface (Fig. 2, top surface of 105c) in contact with the chip interconnect component, and a fourth surface opposite the third surface,
wherein the chip interconnect component includes an electrically conductive frame (Fig. 2, 110,125, 145, etc.; and Paragraph 53-54),
a first side of the electrically conductive frame (Fig. 2, top side of 110) is electrically coupled to the second surface of the first chip, and a second side of the electrically conductive frame (Fig. 2, bottom surface of 110) is electrically coupled to the third surface of the second chip, and
wherein the chip interconnect component includes an insulating material (Fig. 2, 140 and Paragraph 56) in a gap of the electrically conductive frame between the first chip and the second chip.
With respect to claim 2, Wang teaches a first substrate component (Fig. 2, 120a and/or Fig. 9, 530) in contact with the first surface of the first chip, configured to transfer heat from the first surface (Paragraph 69); and
a second substrate component (Fig. 2, 120b and/or Fig. 9, 530) in contact with the fourth surface of the second chip, configured to transfer heat from the fourth surface,
wherein the electrically conductive frame is configured to transfer heat from the second surface of the first chip and transfer heat from the third surface of the second chip (Paragraph 56).
With respect to claim 5, Wang teaches a first sintered layer (Fig. 2, 115 and Paragraph 53) between the first chip and the electrically conductive frame; and a second sintered layer between the second chip and the electrically conductive frame.
With respect to claim 6, Wang teaches that the first chip is a first power transistor (Paragraph 53), the second chip is a second power transistor, and a gate of the first power transistor and a gate of the second power transistor are electrically coupled via a first electrically conductive pillar (Fig. 2, vertical portion of 125; Paragraph 56) of the electrically conductive frame.
With respect to claim 8, Wang teaches that the electrically conductive frame comprises at least one of copper (Paragraph 56), silver, aluminum, or solder material.
With respect to claim 9, Wang teaches that the insulating material is at least one of polyimide, polymethacrylimide, or epoxy resin (Paragraph 56).
With respect to claim 10, Wang teaches a third chip (Fig. 2, 105b or 105d) electrically coupled to the electrically conductive frame of the chip interconnect component, on a same side as the first chip or the second chip, wherein the first substrate component (Fig. 2, 120a and/or Fig. 9, 530) or the second substrate component is in contact with the third chip and is configured to conduct heat from the third chip.
With respect to claim 11, Wang teaches a method, comprising:
coupling a first chip (Fig. 2, 105a) on a first substrate component (Fig. 2, 120a and/or Fig. 9, 530), the first chip having a first surface in contact with the first substrate component, and a second surface opposite the first surface;
forming a chip interconnect component (Fig. 2, 110+140) on the first substrate component and the second surface of the first chip;
coupling a second chip (Fig. 2, 105c) on the chip interconnect component, the second chip having a third surface in contact with the chip interconnect component, and a fourth surface opposite the third surface; and
forming a second substrate (Fig. 2, 120b and/or Fig. 9, 530) component on the fourth surface of the second chip,
wherein the chip interconnect component includes: an electrically conductive frame (Fig. 2, 110,125, 145, etc.; and Paragraph 53-54), a first side of the electrically conductive frame being electrically coupled to the second surface of the first chip, and a second side of the electrically conductive frame being electrically coupled to the third surface of the second chip; and
an insulating material (Fig. 2, 140 and Paragraph 56) for filling a gap of the electrically conductive frame between the first chip and the second chip.
With respect to claim 12, Wang teaches a first substrate component (Fig. 2, 120a and/or Fig. 9, 530) in contact with the first surface of the first chip, configured to transfer heat from the first surface (Paragraph 69); and
a second substrate component (Fig. 2, 120b and/or Fig. 9, 530) in contact with the fourth surface of the second chip, configured to transfer heat from the fourth surface,
wherein the electrically conductive frame is configured to transfer heat from the second surface of the first chip and transfer heat from the third surface of the second chip (Paragraph 56).
With respect to claim 16, Wang teaches that the first chip is a first power transistor (Paragraph 53), the second chip is a second power transistor, and a gate of the first power transistor and a gate of the second power transistor are electrically coupled via a first electrically conductive pillar (Fig. 2, vertical portion of 125; Paragraph 56) of the electrically conductive frame.
With respect to claim 18, Wang teaches that when forming the first chip or forming the second chip, further forming a third chip (Fig. 2, 105b or 105d), the third chip being electrically coupled to the electrically conductive frame of the chip interconnect component.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Kobayashi et al (U.S. Pub #2022/0359336).
With respect to claim 3, Wang does not teach that the first substrate component comprises at least a first positioning member that matches a second positioning member on the insulating material.
Kobayahsi teaches a power device package, wherein a substrate component (Fig. 9, 10) comprises a first positioning member that matches a second positioning member (Fig. 9, 32 and Paragraph 80) on an insulating material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first positioning member and a second positioning member on the insulating material of Wang as taught by Kobayashi in order to achieve the predictable result of positioning the substrate component on the package (Paragraph 80-81).
With respect to claim 4, Wang does not teach that the second substrate component comprises at least a third positioning member that matches a fourth positioning member on the insulating material.
Kobayahsi teaches a power device package, wherein a substrate component (Fig. 9, 10) comprises a first positioning member that matches a second positioning member (Fig. 9, 32 and Paragraph 80) on an insulating material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a third positioning member and a fourth positioning member on the insulating material of Wang as taught by Kobayashi in order to achieve the predictable result of positioning the substrate component on the package (Paragraph 80-81).
With respect to claim 13, Wang does not teach that the first substrate component is includes at least a first positioning member that matches a second positioning member on the insulating material; and wherein the second substrate component includes at least a third positioning member that matches a fourth positioning member on the insulating material.
Kobayahsi teaches a power device package, wherein a substrate component (Fig. 9, 10) comprises a first positioning member that matches a second positioning member (Fig. 9, 32 and Paragraph 80) on an insulating material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first/third positioning member and a second/fourth positioning member on the insulating material of Wang as taught by Kobayashi in order to achieve the predictable result of positioning the substrate component on the package (Paragraph 80-81).
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Nasu (U.S. Pub #2021/0398884).
With respect to claim 7, Wang does not teach that a source of the first power transistor and a source of the second power transistor are electrically coupled via at least one second electrically conductive pillar of the electrically conductive frame.
Nasu teaches a source of the first power transistor and a source of the second power transistor are electrically coupled via at least one second electrically conductive pillar of the electrically conductive frame.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the first and second source of the first and second power transistors of Wang as taught by Nasu in order to implement a common source device, enabling the devices to drive even if the control signal input to the gate terminal have low voltage (Paragraph 107).
With respect to claim 17, Wang does not teach that a source of the first power transistor and a source of the second power transistor are electrically coupled via at least one second electrically conductive pillar of the electrically conductive frame.
Nasu teaches a source of the first power transistor and a source of the second power transistor are electrically coupled via at least one second electrically conductive pillar of the electrically conductive frame.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the first and second source of the first and second power transistors of Wang as taught by Nasu in order to implement a common source device, enabling the devices to drive even if the control signal input to the gate terminal have low voltage (Paragraph 107).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Tolentino et al (U.S. Pub #2021/0225730).
With respect to claim 14, Wang teaches a sintering process (Fig. 2, 115 and Paragraph 53), but does not teach forming the chip interconnect component on the second surface comprises: causing the first chip to be in electrical contact with the electrically conductive frame through a wet sintering process.
Tolentino teaches causing the first chip to be in electrical contact with the electrically conductive frame through a wet sintering process (Paragraph 32-34).
It would have been obvious to one of ordinary skill in the art at before the effectively filing date of the claimed invention to use a wet sintering process as taught by Tolentino in order to achieve the predictable result of sintering the chip to the interconnect.
With respect to claim 15, Wang teaches a sintering process (Fig. 2, 115 and Paragraph 53), but does not teach forming the chip interconnect component on the second surface comprises: causing the second chip to be in electrical contact with the electrically conductive frame through a wet sintering process.
Tolentino teaches causing the first chip to be in electrical contact with the electrically conductive frame through a wet sintering process (Paragraph 32-34).
It would have been obvious to one of ordinary skill in the art at before the effectively filing date of the claimed invention to use a wet sintering process as taught by Tolentino in order to achieve the predictable result of sintering the chip to the interconnect.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Ji et al (U.S. Pub #2021/0210472).
With respect to claim 19,
Wang teaches a semiconductor package, comprising:
a first chip (Fig. 2, 105a and Paragraph 53) having a first surface, and a second surface (Fig. 2, bottom surface) opposite the first surface;
a chip interconnect component (Fig. 2, 110+140) on the second surface of the first chip; and
a second chip (Fig. 2, 105c) on the chip interconnect component, the second chip including a third surface (Fig. 2, top surface of 105c) in contact with the chip interconnect component, and a fourth surface opposite the third surface,
wherein the chip interconnect component includes an electrically conductive frame (Fig. 2, 110,125, 145, etc.; and Paragraph 53-54),
a first side of the electrically conductive frame (Fig. 2, top side of 110) is electrically coupled to the second surface of the first chip, and a second side of the electrically conductive frame (Fig. 2, bottom surface of 110) is electrically coupled to the third surface of the second chip, and
wherein the chip interconnect component includes an insulating material (Fig. 2, 140 and Paragraph 56) in a gap of the electrically conductive frame between the first chip and the second chip.
Wang does not teach a power supply module, comprising: at least two semiconductor packages.
Ji teaches a power supply module, comprising at least two semiconductor packages (Fig. 1A, 20 and Paragraph 54).
It would have been obvious to one of ordinary skill in the art before the effectively filing date of the claimed invention to provide at least two package as taught by Wang as part of a power supply module as taught by Ji in order to implement a two stage power supply (Paragraph 57).
With respect to claim 20, Wang teaches a first substrate component (Fig. 2, 120a and/or Fig. 9, 530) in contact with the first surface of the first chip, configured to transfer heat from the first surface (Paragraph 69); and
a second substrate component (Fig. 2, 120b and/or Fig. 9, 530) in contact with the fourth surface of the second chip, configured to transfer heat from the fourth surface,
wherein the electrically conductive frame is configured to transfer heat from the second surface of the first chip and transfer heat from the third surface of the second chip (Paragraph 56).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812