DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0375781 Lin et al.
1. Referring to claim 1, Lin et al. teaches a semiconductor structure, comprising: a first integrated circuit (IC) component comprising: a first bonding structure, (Figure 2K #134), comprising a first bonding dielectric layer, (Figure 2K #130), and a first bonding feature, (Figure 2K #236 in #130), disposed in the first bonding dielectric layer, (Figure 2K #130); and a first alignment pattern, (Figure 2K #108), disposed in the first bonding dielectric layer, (Figure 2K #130); and a second IC component, (Figure 2K #240), underlying and electrically coupled to the first IC component, (Figure 2K #134), the second IC component, (Figure 2K #240), comprising: a second bonding structure comprising a second bonding dielectric layer, (Figure 2K #246), bonded to the first bonding dielectric layer, (Figure 2K #130), and a second bonding feature, (Figure 2K #236 in #246), disposed in the second bonding dielectric layer, (Figure 2K #246), and bonded to the first bonding feature, (Figure 2K #236 in #130); and a second alignment pattern, (Figure 2K #254 & Paragraph 0049), disposed in the second bonding dielectric layer, (Figure 2K #246), and aligned with the first alignment pattern, (Figure 2K #108), in a staggered manner, (horizontally staggered), but is silent to wherein the second alignment pattern, (Figure 2K #254), is disposed within a boundary of the first IC component, (Figure 2K #134), in a top-down view.
Lin et al. teaches the process of aligning the alignment marks in Figures 1A, 10B, 11B, and 12A-D and in Paragraphs 0019-0022 for other embodiments where the first and second alignment patterns are within the boundary of the upper and lower devices from a plan view.
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to know that the same teachings of Lin et al. for the alignment of devices using the alignment patterns are within the boundary of the upper and lower devices from a plan view would apply to the embodiment of Figure 2K, otherwise it would teach away from the teachings found in Paragraphs 0019-0022. The teachings teach how each of the paired alignment patterns are used using a OVL measurement apparatus and the upper and lower devices are adjusted to be within the specified acceptable ranges.
2. Referring to claim 2, Lin et al. teaches a semiconductor structure of claim 1, wherein bonding surfaces of the first bonding dielectric layer, (Figure 2K #130), and the first bonding feature, (Figure 2K #236 in #130) are substantially leveled with a bonding surface of the first alignment pattern, (Figure 2K #108), which is bonded to the second bonding dielectric layer, (Figure 2K #246).
3. Referring to claim 3, Lin et al. teaches a semiconductor structure of claim 1, wherein bonding surfaces of the second bonding dielectric layer, (Figure 2K #246), and the second bonding feature, (Figure 2K #236 in #246) are substantially leveled with a bonding surface of the second alignment pattern, (Figure 2K #254 & Paragraph 0049), which is bonded to the first bonding dielectric layer, (Figure 2K #130).
4. Referring to claim 17, Lin et al. teaches a manufacturing method of a semiconductor structure, comprising: providing a first IC component, wherein the first IC component comprises: a first bonding structure, (Figure 2K #134), comprising a first bonding dielectric layer, (Figure 2K #130), and a first bonding feature, (Figure 2K #236 in #130), disposed in the first bonding dielectric layer, (Figure 2K #130); and a first alignment pattern, (Figure 2K #108), disposed in the first bonding dielectric layer, (Figure 2K #130); and providing a second IC component, wherein the second IC component comprises: a second bonding structure, (Figure 2K #240), comprising a second bonding dielectric layer, (Figure 2K #246), bonded to the first bonding dielectric layer, (Figure 2K #130), and a second bonding feature, (Figure 2K #236 in #246), disposed in the second bonding dielectric layer, (Figure 2K #246), and bonded to the first bonding feature, (Figure 2K #236 in #130); and a second alignment pattern, (Figure 2K #254 & Paragraph 0049), disposed in the second bonding dielectric layer, (Figure 2K #246); and bonding the first IC component, (Figure 2K #134), to the second IC component, (Figure 2K #240), by using the first, (Figure 2K #108), and second alignment patterns, (Figure 2K #254 & Paragraph 0049), wherein after bonding the first IC component, (Figure 2K #134), to the second IC component, (Figure 2K #240), the second alignment pattern, (Figure 2K #254 & Paragraph 0049), is aligned with the first alignment pattern, (Figure 2K #108), in a staggered manner, but is silent to the second alignment pattern is disposed within a boundary of the first IC component in a top-down view.
Lin et al. teaches the process of aligning the alignment marks in Figures 1A, 10B, 11B, and 12A-D and in Paragraphs 0019-0022 for other embodiments where the first and second alignment patterns are within the boundary of the upper and lower devices from a plan view.
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to know that the same teachings of Lin et al. for the alignment of devices using the alignment patterns are within the boundary of the upper and lower devices from a plan view would apply to the embodiment of Figure 2K, otherwise it would teach away from the teachings found in Paragraphs 0019-0022. The teachings teach how each of the paired alignment patterns are used using a OVL measurement apparatus and the upper and lower devices are adjusted to be within the specified acceptable ranges.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
5. Claims 4-11 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The prior art, (U.S. PUBS No. 2021/0375781), teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the semiconductor structure of claim 1, further comprising: an insulating encapsulant disposed on the second IC component and laterally covering the first IC component; the semiconductor structure of claim 1, wherein the first IC component further comprises a semiconductor substrate disposed over the first bonding structure and a through substrate via penetrating through the semiconductor substrate and electrically coupled to the first bonding feature; the semiconductor structure of claim 1, wherein the first bonding dielectric layer comprises a first portion in which the first bonding feature is disposed and a second portion in which the first alignment pattern is disposed, wherein a thickness of the second portion is less than a thickness of the first portion; the semiconductor structure of claim 1, wherein: the first bonding dielectric layer comprises a first sublayer and a second sublayer connected to the first sublayer and the second bonding dielectric layer, and the first alignment pattern comprises a first-level pattern in the first sublayer and a second-level pattern in the second sublayer and vertically aligned with the first-level pattern; the manufacturing method of claim 17, wherein bonding the first IC component to the second IC component comprises: aligning the first alignment pattern of the first IC component with the second alignment pattern of the second IC component; bring the first bonding feature of the first IC component in contact with the second bonding feature of the second IC component; and annealing the first and second bonding features to form metal-to-metal bonds at a bonding interface of the first and second IC components; the manufacturing method of claim 17, further comprising: forming an insulating encapsulation of the second IC component to laterally cover the first IC component after bonding the first IC component to the second IC component; and/or the manufacturing method of claim 17, wherein providing the first IC component comprises: recessing a region of a bonding dielectric material to form the first bonding dielectric layer comprising a first portion and a second region thinner than the first portion; forming the first bonding feature in the first portion of the first bonding dielectric layer; and forming the first alignment pattern in the second portion of the first bonding dielectric layer.
7. The prior art, (U.S. PUBS No. 2021/0375781), teaches a semiconductor structure, comprising: a first IC component comprising a first functional region, a first alignment region outside the first functional region, and a first alignment pattern disposed within the first alignment region; and a second IC component underlying and electrically coupled to the first IC component, and the second IC component comprising: a second functional region electrically coupled to the first functional region; a second alignment region outside the second functional region and overlapping the first alignment region in a stacking direction of the first and second IC components; and a second alignment pattern disposed within the second alignment region and aligned with the first alignment pattern in a staggered manner in the stacking direction, but is silent to the above teachings in combination with a size of the second IC component being larger than that of the first IC component, and wherein the first and second alignment patterns are electrically floating.
8. These combinations have been found to not be anticipated or render obvious over the prior art, hence claims 12-16 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 3/12/26