DETAILED ACTION
Claim Objections
1. Claims 1, 7, 9 are objected to because of the following informalities:
In claim 1, lines 8, 9, “the source/drain” should be changed to “the first and second source/drain regions” because “the source/drain” is lack of antecedent basis.
In claim 7, line 8, “the source/drain” should be changed to “the first and second source/drain regions” because “the source/drain” is lack of antecedent basis.
In claim 20, line 9, “the source/drain” should be changed to “the first and second source/drain regions” because “the source/drain” is lack of antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1 – 4, 6 – 10, 12, 20 - 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BAE et al. (20220320301).
With regard to claim 1, BAE et al. disclose a semiconductor device (for example, see figs. 13, 15, 20-23), comprising:
a first transistor adjacent to a second transistor (the first region I may be an NMOS region having NMOS transistor, and the second region II may be a PMOS region having PMOS transistor; for example, see paragraph [0032]); and
an etch stop layer (referred to as “130A” by examiner’s annotation shown in fig. 23 below; wherein the etch stop layer 130A is a portion layer of the etch stop layer 130) within an interlayer dialectic (140) configured to separate a lateral contact (contact 862 functions as a lateral contact) and a plurality of backside source/drain region-gate cut dielectric layers (insulating layers 105, 130B as annotated in fig. 23 below wherein the insulating layer 130B is a portion layer of the layer 130; forming on the back of the source/drain regions forming in the active patterns F1, F2, F3, F4 as shown in fig. 23 having separated gates G11, G12 or other gates forming in the PMOS transistor. Therefore, insulating layers 105, 130B surrounding the backside of the source/drain having separated gates functioning as backside source/drain region-gate cut dielectric layers. Although the applicant uses terms different to those of BAE et al. to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements. Applicant’s claim 1 does not distinguish over BAE et al. references regardless of the process “cut” used to form separated gates or discontinued gates G11, G21 or other gates forming in the PMOS transistor because only the final product is relevant);
wherein the lateral contact (862) connects a via (192) over a first source/drain region (a first source/drain region forming in the active patterns F1, F2) of the first transistor to a second source/drain region (a second source/drain region forming in the active patterns F3, F4) of the second transistor;
wherein the plurality of backside source/drain region-gate cut dielectric layers (105, 130B) has a vertical height dimension (the portion layer 130B formed on the top of the source/drain regions 121, 122) that extends from a backside region of the first and second transistors to a height greater than a frontside height of the source/drain (the source/drain regions forming in the active patterns F1, F2, F3, F4).
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With regard to claim 2, BAE et al. disclose the lateral contact (862) is located between the via (192) and the etch stop layer (130).
With regard to claim 3, BAE et al. disclose a contact (122) of the second source/drain region is extended through the etch stop layer (130A).
With regard to claim 4, BAE et al. disclose the contact (122) of the second source/drain region is located between two adjacent backside source/drain region-gate cut dielectric layers (105, 130B).
With regard to claim 6, BAE et al. disclose the lateral contact (862) is located above the first and second source/drain regions (the first and second source/drain regions forming in the active patterns F1, F2, F3, F4).
With regard to claim 7, BAE et al. disclose a semiconductor device (for example, see figs. 13, 15, 23 – 25), comprising:
a first transistor adjacent to a second transistor (the first region I may be an NMOS region having NMOS transistor, and the second region II may be a PMOS region having PMOS transistor; for example, see paragraph [0032]); and
an etch stop layer (referred to as “130A” by examiner’s annotation shown in fig. 23 below; wherein the etch stop layer 130A is a portion layer of the etch stop layer 130) within an interlayer dialectic (140) configured to separate a lateral contact (contact 862 functions as a lateral contact) and a plurality of backside source/drain region-gate cut dielectric layers (insulating layers 105, 130B as annotated in fig. 23 below wherein the insulating layer 130B is a portion layer of the layer 130; forming on the back of the source/drain regions forming in the active patterns F1, F2, F3, F4 as shown in fig. 23 having separated gates G11, G12 or other gates forming in the PMOS transistor. Therefore, insulating layers 105, 130B surrounding the backside of the source/drain having separated gates functioning as backside source/drain region-gate cut dielectric layers. Although the applicant uses terms different to those of BAE et al. to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements. Applicant’s claim 1 does not distinguish over BAE et al. references regardless of the process “cut” used to form separated gates or discontinued gates G11, G21 or other gates forming in the PMOS transistor because only the final product is relevant);
wherein a contact (861) of a first source/drain region (a source/drain region forming in the active patterns F1, F2) is extended through the etch stop layer (130A);
wherein the plurality of backside source/drain region-gate cut dielectric layers (105, 130B) has a vertical height dimension (the portion layer 130B formed on the top of the source/drain regions 121, 122) that extends from a backside region of the first and second transistors to a height greater than a frontside height of the source/drain (the source/drain regions forming in the active patterns F1, F2, F3, F4).
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With regard to claim 8, BAE et al. disclose the lateral contact (862) connects a via (192) over a second source/drain region (a second source/drain region forming in the active patterns F1, F2) of the first transistor to a second source/drain region (a second source/drain region forming in the active patterns F3, F4) of the second transistor.
With regard to claim 9, BAE et al. disclose the lateral contact (862) is located between the via (192) and the etch stop layer (130A).
With regard to claim 10, BAE et al. disclose the contact (121) of the first source/drain region is located between two adjacent backside source/drain region-gate cut dielectric layers (105, 130A).
With regard to claim 12, BAE et al. disclose the lateral contact (862) is located above the first and second source/drain regions (the first and second source/drain regions forming in the active patterns F1, F2, F3, F4).
With regard to claim 20, BAE et al. disclose a semiconductor device (for example, see figs. 23 – 25), comprising:
a first transistor adjacent to a second transistor (the first region I may be an NMOS region having NMOS transistor, and the second region II may be a PMOS region having PMOS transistor; for example, see paragraph [0032]); and
an etch stop layer (referred to as “130A” by examiner’s annotation shown in fig. 23 below; wherein the etch stop layer 130A is a portion layer of the etch stop layer 130) within an interlayer dialectic (140); and
a contact (861) extending through the etch stop layer (130A) to connect a source/drain region (a source/drain region forming in the active patterns F1, F2) to a back end of line (a region line AR1 or a conductive substrate 100 functions as a back end of line; for example, see paragraph [0031]);
a plurality of backside source/drain region-gate cut dielectric layers (insulating layers 105, 130B as annotated in fig. 23 below wherein the insulating layer 130B is a portion layer of the layer 130; forming on the back of the source/drain regions forming in the active patterns F1, F2, F3, F4 as shown in fig. 23 having separated gates G11, G12 or other gates forming in the PMOS transistor. Therefore, insulating layers 105, 130B surrounding the backside of the source/drain having separated gates functioning as backside source/drain region-gate cut dielectric layers. Although the applicant uses terms different to those of BAE et al. to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements. Applicant’s claim 1 does not distinguish over BAE et al. references regardless of the process “cut” used to form separated gates or discontinued gates G11, G21 or other gates forming in the PMOS transistor because only the final product is relevant);
wherein the plurality of backside source/drain region-gate cut dielectric layers (105, 130B) has a vertical height dimension (the portion layer 130B formed on the top of the source/drain regions 121, 122) that extends from a backside region of the first and second transistors to a height greater than a frontside height of the source/drain (the source/drain regions forming in the active patterns F1, F2, F3, F4);
wherein a side surface of the contact (861) is in direct contact with one (130B) of the plurality of backside source/drain region-gate cut dielectric layers (130B, 105).
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With regard to claim 21, BAE et al. disclose the ILD (140) is configured to separate a lateral contact (862) and a plurality of backside source/drain region-gate cut dielectric layers (105, 130B), wherein the lateral contact (862) connects a via (192) over a first source/drain region (a first source/drain region forming in the active patterns F1, F2) of the first transistor to a second source/drain region (a second source/drain region forming in the active patterns F3, F4) of the second transistor.
With regard to claim 22, BAE et al. disclose the lateral contact (862) is located between the via (192) and the etch stop layer (130A).
With regard to claim 23, BAE et al. disclose the lateral contact (862) is located above the first and second source/drain regions (the first and second source/drain regions forming in the active patterns F1, F2, F3, F4).
With regard to claim 24, BAE et al. disclose another contact (862) of another source/drain region (another source/drain region forming in the active patterns F3, F4) is extended through the etch stop layer (130A).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 5, 11, 25 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al. (20220320301) in view of YU (20220359685).
With regard to claims 5, 25, BAE et al. disclose the first source/drain region is connected to a backside power rail through a direct backside contact.
However, YU discloses the first source/drain region (one of the source/drain regions 110B, forming in an array, functions as the first source/drain region) is connected to a backside power rail (103) through a direct backside contact (contacts 148, 104 function as a direct backside contact). (for example, see fig. 2A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the BAE et al.’s device to have the first source/drain region is connected to a backside power rail through a direct backside contact as taught by YU in order to secure the electrical connection power for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 11, BAE et al. disclose the second source/drain region is connected to a backside power rail through a direct backside contact.
However, YU discloses the second source/drain region (one of the source/drain regions 110B, forming in an array, functions as the second source/drain region) is connected to a backside power rail (103) through a direct backside contact (contacts 148, 104 function as a direct backside contact). (for example, see fig. 2A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the BAE et al.’s device to have the second source/drain region is connected to a backside power rail through a direct backside contact as taught by YU in order to secure the electrical connection power for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Amendment
6. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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